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TPS54821

SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016

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7 Detailed Description

7.1 Overview

The device is a 17-V, 8-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To

improve performance during line and load transients the device implements a constant frequency, peak current

mode control which also simplifies external frequency compensation. The wide switching frequency of 200 kHz to

1600 kHz allows for efficiency and size optimization when selecting the output filter components. The switching

frequency is adjusted using a resistor to ground on the RT/CLK pin. The device also has an internal phase lock

loop (PLL) controlled by the RT/CLK pin that can be used to synchronize the switching cycle to the falling edge

of an external system clock.

The device has been designed for safe monotonic startup into pre-biased loads. The default start up is when VIN

is typically 4.0V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage

under voltage lockout (UVLO) with two external resistors. In addition, the EN pin can be floating for the device to

operate with the internal pull-up current. The total operating current for the device is approximately 600

μA when

not switching and under no load. When the device is disabled, the supply current is typically less than 2

μA.

The integrated MOSFETs allow for high efficiency power supply designs with continuous output currents up to 8

amperes. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications.

The device reduces the external component count by integrating the boot recharge circuit. The bias voltage for

the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor

voltage is monitored by a BOOT to PH UVLO (BOOT-PH UVLO) circuit allowing PH pin to be pulled low to

recharge the boot capacitor. The device can operate at 100% duty cycle as long as the boot capacitor voltage is

higher than the preset BOOT-PH UVLO threshold which is typically 2.1V. The output voltage can be stepped

down to as low as the 0.6V voltage reference (Vref).

The device has a power good comparator (PWRGD) with hysteresis which monitors the output voltage through

the VSENSE pin. The PWRGD pin is an open drain MOSFET which is pulled low when the VSENSE pin voltage

is less than 92% or greater than 106% of the reference voltage Vref and asserts high when the VSENSE pin

voltage is 94% to 104% of the Vref.

The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing

during power up. A small value capacitor or resistor divider should be coupled to the pin for slow start or critical

power supply sequencing requirements.

The device is protected from output overvoltage, overload and thermal fault conditions. The device minimizes

excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator.

When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning

on until the VSENSE pin voltage is lower than 104% of the Vref. The device implements both high-side MOSFET

overload protection and bidirectional low-side MOSFET overload protections which help control the inductor

current and avoid current runaway. The device also shuts down if the junction temperature is higher than thermal

shutdown trip point. The device is restarted under control of the slow start circuit automatically after the built-in

thermal shutdown hiccup time.