7.3 Power Supply Recommendations

Power to the device is supplied through the VCC pin. TI recommends placing a bypass capacitor as close as

possible to the supply pin VCC to help smooth out lower frequency noise to provide better load regulation across

the frequency spectrum.

This device does not require any power sequencing with respect to other devices in the system due to the power

off isolation feature. The power off isolation feature allows signals to be present on the signal path pins before

the device is powered up without damaging the device.

7.4 Layout

7.4.1 Layout Guidelines

Place supply bypass capacitors as close to the VCC pin as possible and avoid placing the bypass caps near the

D+ and D– traces.

The high-speed D+ and D– traces must always be of equal length and must be no more than four inches;

otherwise, the eye diagram performance may degrade. A high-speed USB connection is made through a

shielded, twisted pair cable with a differential characteristic impedance. In the layout, the impedance of D+ and

D– traces must match the cable characteristic differential impedance for optimal performance.

Route the high-speed USB signals using a minimum of vias and corners which reduces signal reflections and

impedance changes. When a via must be used, increase the clearance size around the via to minimize the

capacitance. Each via introduces discontinuities in the transmission line of the signal and increases the chance

of picking up interference from the other layers of the board. Be careful when designing test points on twisted

pair lines; through-hole pins are not recommended.

When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This

reduces reflections on the signal traces by minimizing impedance discontinuities.

Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,

mounting holes, magnetic devices, or ICs that use or duplicate clock signals.

Avoid stubs on the high-speed USB signals because the stubs cause signal reflections. If a stub is unavoidable,

then the stub must be less than 200 mm.

Route all high-speed USB signal traces over continuous GND planes, with no interruptions.

Avoid crossing over anti-etch, commonly found with plane splits.

Due to high frequencies associated with the USB, a printed circuit board with at least four layers is

recommended: two signal layers separated by a ground layer and a power layer. The majority of signal traces

must run on a single layer, preferably top layer. Immediately next to this layer must be the GND plane, which is

solid with no cuts. Avoid running signal traces across a split in the ground or power plane. When running across

split planes is unavoidable, sufficient decoupling must be used. Minimizing the number of signal vias reduces

EMI by reducing inductance at high frequencies. For more information on layout guidelines, see High Speed

Layout Guidelines and USB 2.0 Board Design and Layout Guidelines.

www.ti.com

TS3USB3031

SCDS348D – SEPTEMBER 2013 – REVISED AUGUST 2024

Copyright © 2024 Texas Instruments Incorporated

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Product Folder Links: TS3USB3031