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TUSB7340RKMT Datasheet(PDF) 22 Page - Texas Instruments |
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TUSB7340RKMT Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 122 page ![]() Table 6-4. EEPROM Register Loading Map (continued) SERIAL EEPROM WORD ADDRESS BYTE DESCRIPTION 16h PCI ECh, Custom PHY Transmit/Receive Control, Byte 0 17h PCI EDh, Custom PHY Transmit/Receive Control, Byte 1 18h PCI EEh, Custom PHY Transmit/Receive Control, Byte 2 19h PCI EFh, Custom PHY Transmit/Receive Control, Byte 3 1Ah PCI 61h, Frame Length Adjustment Register 1Bh End of List Indicator (80h) This format must be explicitly followed for the host controller to correctly load initialization values from a serial EEPROM. All byte locations must be considered when programming the EEPROM. The serial EEPROM is addressed by the host controller at target address 1010 000b. This target address is internally hardwired and cannot be changed by the system designer. Therefore, all three hardware address bits for the EEPROM are tied to VSS to achieve this address. The serial EEPROM in the sample application circuit (Figure 6-2) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to VSS. During an EEPROM download operation, bit 4 (ROMBUSY) in the serial-bus control and status register is asserted. After the download is finished, bit 0 (ROM_ERR) in the serial-bus control and status register may be monitored to verify a successful download. 6.4.2 System Management Interrupt The TUSB73X0 includes a System Management Interrupt (SMI) pin to allow for USB support in the BIOS of a system that implements the TUSB73X0. The SMI pin is controlled by the bits in the USB Legacy Support Control/Status Register. See USB Legacy Support Control/Status Register for more information. If there are no SMI events pending or if all sources for SMI are disabled, the TUSB73X0 drives the SMI pin low. When an SMI event occurs and the corresponding event is enabled, the TUSB73X0 drives the SMI pin high until the event is cleared or disabled. TUSB7320, TUSB7340 SLLSE76Q – MARCH 2011 – REVISED MARCH 2024 www.ti.com 22 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TUSB7320 TUSB7340 |
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