DM505LRBABF datasheet(123/295 Pages) TI2

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DM505

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SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

5.9.6.6.1 GPMC/NOR Flash Interface Synchronous Timing

Table 5-33 and Table 5-34, Table 5-35 and Table 5-36 assume testing over the recommended operating

conditions and electrical characteristic conditions below (see Figure 5-22, Figure 5-23, Figure 5-24,

Figure 5-25, Figure 5-26 and Figure 5-27).

Table 5-33. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 1 Load

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

F12

tsu(dV-clkH)

Setup time, read gpmc_ad[15:0] valid before gpmc_clk high

1.9

F13

th(clkH-dV)

Hold time, read gpmc_ad[15:0] valid after gpmc_clk high

F21

tsu(waitV-clkH)

Setup time, gpmc_wait[1:0] valid before gpmc_clk high

1.9

F22

th(clkH-waitV)

Hold Time, gpmc_wait[1:0] valid after gpmc_clk high

NOTE

Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of

wait monitoring feature, see the Device TRM.

Table 5-34. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 1 Load

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tc(clk)

Cycle time, output clock gpmc_clk period (12)

11.3

td(clkH-nCSV)

Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition (14)

F-0.8

F+3.1

td(clkH-nCSIV)

Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid (14)

E-0.8

E+3.1

td(ADDV-clk)

Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge

B-0.8

B+3.1

td(clkH-ADDIV)

Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus

invalid

-0.8

td(nBEV-clk)

Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge

B-3.8

B+1.1

td(clkH-nBEIV)

Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid

D-0.4

D+1.1

td(clkH-nADV)

Delay time, gpmc_clk rising edge to gpmc_advn_ale transition (14)

G-0.8

G+3.1

td(clkH-nADVIV)

Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid (14)

D-0.8

D+3.1

F10

td(clkH-nOE)

Delay time, gpmc_clk rising edge to gpmc_oen_ren transition (14)

H-0.8

H+2.1

F11

td(clkH-nOEIV)

Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid (14)

E-0.8

E+2.1

F14

td(clkH-nWE)

Delay time, gpmc_clk rising edge to gpmc_wen transition (14)

I-0.8

I+3.1

F15

td(clkH-Data)

Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus

transition

J-1.1

J+3.92

F17

td(clkH-nBE)

Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition

J-1.1

J+3.8

F18

tw(nCSV)

Pulse duration, gpmc_cs[7:0] low

F19

tw(nBEV)

Pulse duration, gpmc_ben[1:0] low

F20

tw(nADVV)

Pulse duration, gpmc_advn_ale low

F23

td(CLK-GPIO)

Delay time, gpmc_clk transition to gpio6_16.clkout0 transition (13)

1.2

6.1

Table 5-35. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 5 Loads

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

F12

tsu(dV-clkH)

Setup time, read gpmc_ad[15:0] valid before gpmc_clk high

2.5

F13

th(clkH-dV)

Hold time, read gpmc_ad[15:0] valid after gpmc_clk high

1.9

F21

tsu(waitV-clkH)

Setup time, gpmc_wait[1:0] valid before gpmc_clk high

2.5

F22

th(clkH-waitV)

Hold Time, gpmc_wait[1:0] valid after gpmc_clk high

1.9

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