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DM505LRBABF Datasheet(PDF) 121 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 121 Page - Texas Instruments |
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121 / 295 page  121 DM505 www.ti.com SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 Submit Documentation Feedback Specifications Copyright © 2016–2018, Texas Instruments Incorporated 5.9.6.4 ISS NOTE For more information, see the Imaging Subsystem chapter of the device TRM. The imaging subsystem (ISS) deals with the processing of the pixel data coming from an external image sensor or data from memory (image format encoding and decoding can be done to and from memory). With its subparts, such as interfaces and interconnects, image signal processor (ISP), and still image coprocessor (SIMCOP), the ISS is a key component for the following use cases: • Rear View Camera • Front View Stereo Camera • Surround View Camera The ISS is mainly composed of CAL_A, CAL_B, LVDS-RX camera interfaces, a parallel interface (CPI), an ISP, and a block-based imaging accelerator (SIMCOP). • The Camera Adapter Layer (CAL_A) supports MIPI® CSI2 protocol with four data lanes. The CAL_A is targeted as sensor capture interface and write DMA, while CAL_B is targeted as read DMA engine and does not support sensor capture. • The LVDS receiver (LVDS-RX) support Sony / Aptina / Omnivision / Panasonic / AltaSens serial interfaces. • The parallel interface (CPI) supports up to 16 data lanes. All interfaces can use the image signal processor (ISP), but not concurrently. When one interface uses the ISP, the other must send data to memory. However, the ISP can still be used to process this data in memory-to-memory. Time multiplex processing is also possible. The camera adaptation layer (CAL) deals with the processing of the pixel data coming from an external image sensor, data from memory. The CAL is a key component for the following multimedia applications: camera viewfinder, video record, and still image capture. The CAL has two serial camera interfaces (primary and secondary): • The primary serial interface (CSI2 Port A) is compliant with MIPI CSI-2 protocol with four data lanes. 5.9.6.4.1 CSI-2 MIPI D-PHY—1.5 V and 1.8 V The CSI-2 port A is compliant with the MIPI D-PHY RX specification v1.00.00 and the MIPI CSI-2 specification v1.00, with 4 data differential lanes plus 1 clock differential lane in synchronous mode, double data rate: • 1.5 Gbps (750 MHz) @OPP_NOM for each lane. CAUTION The IO timings provided in this section are only valid if signals within a single IOSET are used. The IOSETs are defined in Table 5-32. In Table 5-32 are presented the specific groupings of signals (IOSET) for use with ISS. Table 5-32. Camera Parallel Interface (CPI) IOSETs SIGNALS IOSET1 IOSET2 BALL MUX BALL MUX cpi_pclk F22 1 F22 1 cpi_data0 F19 1 F19 1 cpi_data1 G19 1 G19 1 |
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