DM505LRBABF datasheet(117/295 Pages) TI2

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vinx_clki

(positive-edge clocking)

vinx_d[23:0]/sig

vinx_clki

(negative-edge clocking)

SPRS8xx_VIP_02

vinx_clki

SPRS91v_VIP_01

117

DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

5.9.6.2

VIP

The device includes 1 Video Input Ports (VIP).

Table 5-28, Figure 5-19 and Figure 5-20 present timings and switching characteristics of the VIPs.

Table 5-28. Timing Requirements for VIP (1)(2)

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tc(CLK)

Cycle time, vinx_clki(3)(5)

5.99 (1)

tw(CLKH)

Pulse duration, vinx_clki high(3)(5)

0.45×P (2)

tw(CLKL)

Pulse duration, vinx_clki low(3)(5)

0.45×P (2)

tsu(CTL/DATA-CLK)

Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi,

vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition (3)(4)(5)

2.52

th(CLK-CTL/DATA)

Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi,

vinx_hsynci) and Data (vinx_dn) valid from vinx_clki transition(3)(4)(5)

-0.05

(1) For maximum frequency of 165 MHz.

(2) P = vinx_clki period.

(3) x in vinx = 1a, 1b, 2a and 2b.

(4) n in dn = 0 to 7 when x = 1b, 2b;

n = 0 to 23 when x = 1a and 2a;

(5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1.

Figure 5-19. Video Input Ports Clock Signal

Figure 5-20. Video Input Ports Timings

CAUTION

The IO timings provided in this section are only valid for VIN1 and VIN2 if

signals within a single IOSET are used. The IOSETs are defined in Table 5-29

and Table 5-30.

In Table 5-29 and Table 5-30 are presented the specific groupings of signals (IOSET) for use with vin1a,

vin1b, vin2a and vin2b.

DM505LRBABF Datasheet(PDF) 117 Page - Texas Instruments

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