ISO6442FDFPR datasheet(18/56 Pages) TI2

18 / 56 page

6.16 Switching Characteristics—3.3V Supply

VCC1 = VCC2 = 3.3V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPLH, tPHL

Propagation delay time

at 100kbps

See Section 7

PWD

Pulse width distortion(1) |tPHL – tPLH|

0.35

2.2

tsk(o)

Channel-to-channel output skew time(2)

Same-direction channels

1.5

tsk(pp)

Part-to-part skew time(3)

Output signal rise time

See Section 7

Output signal fall time

tPHZ

Disable propagation delay, high-to-high impedance output

See Section 7

tPLZ

Disable propagation delay, low-to-high impedance output

tPZH

Enable propagation delay, high impedance-to-high output for

device with EN

See Section 7

tPZL

Enable propagation delay, high impedance-to-low output for

device with EN

tPU

Time from VCC UVLO to valid output data

VCC ramp < 1µs

µs

tDO

Default output delay time from input power loss

Measured from the time VCC goes

below VCC_UVLO–(MIN). See Section 7

0.045

0.1

µs

tie

Time interval error

216 – 1 PRBS data at 100Mbps

0.2

(1)

Also known as pulse skew.

(2)

tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same

direction while driving identical loads.

(3)

tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

ISO6440, ISO6441, ISO6442

SLLSG01B – SEPTEMBER 2024 – REVISED NOVEMBER 2025

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