ISO6442FDFPR datasheet(32/56 Pages) TI2

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9.3 Power Supply Recommendations

To provide reliable operation at data rates and supply voltages, a 0.1μF bypass capacitor is recommended at

the input and output supply pins (VCC1 and VCC2). The capacitors must be placed as close to the supply pins

as possible. If only a single primary-side power supply is available in an application, isolated power can be

generated for the secondary-side with the help of a transformer driver. For industrial applications, please use

Texas Instruments' SN6501 or SN6505B. For such applications, detailed power supply design and transformer

selection recommendations are available in SN6501 Transformer Driver for Isolated Power Supplies or SN6505B

Low-noise, 1A Transformer Drivers for Isolated Power Supplies .

9.4 Layout

9.4.1 Layout Guidelines

A minimum of two layers is required to accomplish a cost optimized and low EMI PCB design. To further

improve EMI, a four layer board can be used (see Layout Example Schematic ). Layer stacking for a four layer

board must be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and

low-frequency signal layer.

• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of the

inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits

of the data link.

• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100pF/inch2.

• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

typically have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system

to the stack to keep the planes symmetrical. This design makes the stack mechanically stable and prevents

warping. Also the power and ground plane of each power system can be placed closer together, thus increasing

the high-frequency bypass capacitance significantly.

For detailed layout recommendations, refer to the Digital Isolator Design Guide application note.

ISO6440, ISO6441, ISO6442

SLLSG01B – SEPTEMBER 2024 – REVISED NOVEMBER 2025

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ISO6442FDFPR Datasheet(PDF) 32 Page - Texas Instruments