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ISO6442FDFPR Datasheet(PDF) 9 Page - Texas Instruments |
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ISO6442FDFPR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 56 page ![]() PARAMETER TEST CONDITIONS PACKAGE UNIT 16-DW RIO Insulation resistance, input to output(6) VIO = 500V, TA = 25°C >1012 Ω VIO = 500V, 100°C ≤ TA ≤ 125°C >1011 VIO = 500V at TS = 150°C >109 Pollution degree 2 Climatic category 40/125/21 UL 1577 VISO Withstand isolation voltage VTEST = VISO , t = 60s (qualification); VTEST = 1.2 ≤ VISO , t = 1s (100% production) 5000 VRMS (1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications. (2) This digital isolator is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. (3) Testing is carried out in air to determine the surge immunity of the package. (4) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier. (5) Apparent charge is electrical discharge caused by a partial discharge (pd). (6) All pins on each side of the barrier tied together creating a two-pin device. www.ti.com ISO6440, ISO6441, ISO6442 SLLSG01B – SEPTEMBER 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: ISO6440 ISO6441 ISO6442 |
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