ADIS16060

Rev. 0 | Page 5 of 12

TIMING SPECIFICATIONS

Table 2. Read/Output Sequence

Parameter

Figure Reference

Symbol

Min

Typ

Max

Unit

Serial Clock Frequency

2.9

MHz

Throughput Rate

See Figure 2

100

kHz

MSEL1 Falling to SCLK Low

See Figure 2

0

μs

MSEL1 Falling to SCLK Rising

See Figure 2

20

ns

SCLK Falling to Data Remains Valid

See Figure 2

5

16

ns

See Figure 2

14

100

ns

SCLK Falling to Data Valid

See Figure 2

16

50

ns

Acquisition Time

See Figure 2

400

ns

See Figure 2

11

25

ns

See Figure 2

11

25

ns

Data Setup Time

See Figure 3

5

5

ns

SCLK Falling Edge to MSEL2 Rising Edge

See Figure 3

0

0

ns

Data Hold Time

See Figure 3

4.5

ns

4.75 V to 5.25 V.

Timing Diagrams

DOUT

SCLK

COMPLETE CYCLE

POWER DOWN

MSEL1

D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

(MSB)

(LSB)

HIGH-Z

0

HIGH-Z

0

14

5

NOTE:

A MINIMUM OF 20 CLOCK CYCLES ARE REQUIRED FOR 14-BIT CONVERSION.

Figure 2. Serial Interface Timing Diagram–Read/Output Sequence (CPOL = 0, CPHA = 0)

DB7

MSEL2

SCLK

DIN

NOTE:

THE LAST EIGHT BITS CLOCKED IN ARE LATCHED WITH THE RISING EDGE OF THE MSEL2 LINE.

DB6 DB5 DB4 DB3 DB2 DB1 DB0

Figure 3. Serial interface Timing–Input/Configuration Sequence (CPOL = 0, CPHA = 1)