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ADIS16060/PCBZ Datasheet(PDF) 10 Page - Analog Devices

Part # ADIS16060/PCBZ
Description  Wide Bandwidth Yaw Rate Gyroscope with SPI
PDF  12 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADIS16060/PCBZ Datasheet(HTML) 10 Page - Analog Devices

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ADIS16060
Rev. 0 | Page 10 of 12
BASIC OPERATION
The ADIS16060 is designed for simple integration into indus-
trial system designs, requiring only a 5 V power supply, two
mode select lines, and three serial communications lines. The
SPI handles all digital I/O communication in the ADIS16060.
SERIAL PERIPHERAL INTERFACE (SPI)
The ADIS16060 SPI port includes five signals: Mode Select 1
(MSEL1), Mode Select 2 (MSEL2), serial clock (SCLK), data
input (DIN), and data output (DOUT). The MSEL1 line is used
when reading data out of the sensor (DOUT), and the MSEL2
line is used when configuring the sensor (DIN).
Selecting Output Data
Refer to Table 5 to determine the appropriate DIN bit sequence
based on the required data source. Table 2 and Figure 3 provide
the necessary timing details for the input configuration sequence.
After the MSEL2 goes high, the last eight DIN bits are loaded
into the internal control register, which represents DB0 to DB7
in Table 5.
Output Data Access
Use Table 2 and Figure 2 to determine the appropriate timing
considerations for reading output data.
OUTPUT DATA FORMATTING
All of the output data is in an offset-binary format, which in
this case, means that the ideal output for a zero rate condition is
8192 codes. If the sensitivity is equal to +0.0122°/sec/LSB, a rate
of +10°/sec results in a change of 820 codes, and a digital rate
output of 9012 codes. If an offset error of −20°/sec is introduced,
the output is reduced by 1639 codes (if typical sensitivity is
assumed), resulting in a digital rate output of 6552 codes.
ADC CONVERSION
The internal successive approximation ADC begins the conversion
process on the falling edge of MSEL1 and starts to place data
MSB first on the DOUT line at the 6th falling edge of SCLK, as
shown in Figure 2. The entire conversion process takes 20 SCLK
cycles. After MSEL1 goes high, the acquisition process starts in
preparation for the next conversion cycle.
Table 5. DIN Configuration Bit Assignments
Action
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Measure Angular Rate (Gyro)
0
0
1
0
0
0
0
0
Measure Temperature
0
0
0
1
0
0
0
0
Measure AIN2
1
0
0
0
0
0
0
0
Measure AIN1
0
1
0
0
0
0
0
0
Set Positive Self-Test and Output for Angular Rate
0
0
1
0
0
0
1
0
Set Negative Self-Test and Output for Angular Rate
0
0
1
0
0
0
0
1



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