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MPF0900AMBA2ES Datasheet(PDF) 201 Page - NXP Semiconductors |
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MPF0900AMBA2ES Datasheet(HTML) 201 Page - NXP Semiconductors |
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201 / 205 page ![]() NXP Semiconductors PF09 Nine-channel power management IC with advanced system safety monitoring Tab. 106. VDIG overvoltage status ................................. 91 Tab. 107. VAON output voltage .......................................91 Tab. 108. VAON modes .................................................. 91 Tab. 109. VAON electrical characteristics ....................... 92 Tab. 110. SW1 output voltage configuration bits .............93 Tab. 111. DVS ramp selection bits ..................................93 Tab. 112. DVS ramp-down selection bits ........................ 94 Tab. 113. Maximum DVS selection bits .......................... 94 Tab. 114. Minimum DVS selection bits ........................... 95 Tab. 115. Mode selection in RUN ................................... 95 Tab. 116. Mode selection in STANDBY .......................... 95 Tab. 117. Default SW1 mode selection during STANDBY ........................................................96 Tab. 118. Current limit selection bits ...............................96 Tab. 119. SW1 phase shift selection bits ........................ 96 Tab. 120. Load switch mode selection bit ....................... 97 Tab. 121. SW1LS control bits ......................................... 97 Tab. 122. SW1LS default STANDBY configuration ......... 97 Tab. 123. SW1LS overcurrent protection bit ................... 98 Tab. 124. SW1 electrical characteristics ......................... 98 Tab. 125. Recommended external components. ...........101 Tab. 126. SW2 voltage setting ...................................... 101 Tab. 127. SWx ramp-down configuration ...................... 102 Tab. 128. Ramp-down DVS ...........................................102 Tab. 129. SWx high-voltage delta ................................. 102 Tab. 130. SW1 low-voltage delta .................................. 103 Tab. 131. Mode selection in RUN ................................. 104 Tab. 132. Mode selection in STANDBY .........................104 Tab. 133. Default SWx mode selection in STANDBY .... 104 Tab. 134. Current limit selection bits .............................104 Tab. 135. SWx phase shift selection bits ...................... 104 Tab. 136. SW2 and SW3 multiphase configuration bits .................................................................105 Tab. 137. SW4 and SW5 multiphase configuration bits .................................................................105 Tab. 138. SW2 - SW5 electrical characteristics .............106 Tab. 139. SWx recommended external components. ....109 Tab. 140. LDO1 output control in RUN ......................... 110 Tab. 141. LDO1 output control in STANDBY .................110 Tab. 142. LDO1 output voltage selection bits ................110 Tab. 143. LDO1 soft-start selection bit ..........................111 Tab. 144. LDO1 load switch selection mode .................111 Tab. 145. LDO1 electrical characteristics ......................112 Tab. 146. LDO1 recommended external components. ..113 Tab. 147. LDOx output control in RUN ......................... 114 Tab. 148. LDOx output control in STANDBY .................114 Tab. 149. LDOx output voltage selection bits ................114 Tab. 150. LDOx soft-start selection bit .......................... 115 Tab. 151. LDOx load switch selection mode ................. 115 Tab. 152. VLDOxMON blanking time configuration bits .................................................................117 Tab. 153. VLDOxMON masking timer ...........................117 Tab. 154. LDO2/LDO3 electrical characteristics ............119 Tab. 155. Recommended external components. ...........121 Tab. 156. SWx UV threshold configuration bits .............122 Tab. 157. SWx OV threshold configuration bits .............123 Tab. 158. SWx UV threshold configuration bits during STANDBY ......................................................123 Tab. 159. SWx OV threshold configuration bits during STANDBY ......................................................123 Tab. 160. LDOx UV threshold configuration bits ........... 124 Tab. 161. LDOx OV threshold configuration bits ........... 124 Tab. 162. Hysteresis on 2.5 % OV/UV threshold configuration bits ........................................... 124 Tab. 163. OV debounce time configuration bits .............125 Tab. 164. UV debounce time configuration bits .............125 Tab. 165. VAON UV threshold configuration bits ...........126 Tab. 166. VAON OV threshold configuration bits .......... 127 Tab. 167. VMONx UV threshold configuration bits ........ 127 Tab. 168. VMONx OV threshold configuration bits ........128 Tab. 169. VMONx UV threshold selection in STANDBY ......................................................128 Tab. 170. VMONx OV threshold selection in STANDBY ......................................................128 Tab. 171. VMONx monitoring voltage configuration bits .................................................................129 Tab. 172. VMONx masking timer configuration bits .......130 Tab. 173. VMONx enable bit .........................................131 Tab. 174. VMONx settling time configuration bits ..........131 Tab. 175. LDOx control bits in VMON mode ................. 131 Tab. 176. VLDOxMON monitoring voltage configuration bits ........................................... 131 Tab. 177. VLDOxMON masking timer configuration bits .................................................................132 Tab. 178. VLDOxMON enable bit ..................................133 Tab. 179. VLDOxMON settling time configuration bits .. 133 Tab. 180. Voltage monitor electrical characteristics .......134 Tab. 181. Manual frequency tuning ...............................136 Tab. 182. Frequency spread spectrum enable bit ......... 136 Tab. 183. Frequency spread spectrum center frequency selection bits .................................136 Tab. 184. Spread-spectrum mode selection bit .............137 Tab. 185. FSYNC mode selection bit ............................138 Tab. 186. Enabling FSYNC output frequency enable bit ...................................................................138 Tab. 187. FSYNC input frequency range selection bit ...139 Tab. 188. FSYNC electrical characteristics ................... 139 Tab. 189. AMUX enable bit ........................................... 140 Tab. 190. AMUX channel selection ............................... 140 Tab. 191. AMUX electrical characteristics .....................141 Tab. 192. Thermal thresholds notification bits ...............143 Tab. 193. Thermal monitoring electrical characteristics ................................................144 Tab. 194. Bandgap monitor status bit ........................... 147 Tab. 195. System watchdog enable bit ......................... 148 Tab. 196. System watchdog timer configuration bits ..... 149 Tab. 197. System watchdog window configuration bits .................................................................150 Tab. 198. WD_OK events required to reduce the Fault counter by 1 .........................................152 Tab. 199. FS0B status bit ..............................................154 Tab. 200. ERRMON polarity selection bit ......................155 Tab. 201. ERRMON timer configuration bit ................... 156 Tab. 202. ERRMON reaction configuration bit .............. 156 Tab. 203. ERRMON dynamic characteristics ................ 156 Tab. 204. FCCU0 mode selection bits .......................... 157 Tab. 205. FCCU1 mode selection bit ............................ 157 PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback 201 / 205 |
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