When PR is clocked, the PR pulse must be damped to pro-
duce a smooth PR pulse. If PR switches too rapidly, the uni-
formity of the OS signal will be affected by the PR clock
feedthrough. A current-drive PR clock circuit generally in-
troduces less feedthrough than a voltage-drive circuit.
Antiblooming is always present when biases fall within the
specified operating conditions. By adjusting VSTOR how-
ever, the user has the added flexibility of selecting the anti-
blooming level (the signal level beyond which the additional
signal charge is drained away). A higher VSTOR bias results
in a higher antiblooming level.
Transfer
The TCK clock controls the transfer of electrons from the
storage well into the 2-phase buried-channel CCD readout
register. Transfer is from the storage wells into the CR1
phases of the readout register. The readout register is then
used to serially shift the charge packets to the high-speed
low-noise output amplifier.
The final phase of the readout register is connected sepa-
rately to CRLAST. This provides the flexibility of timing the
transfer of signal charges to the output node. CRLAST is
normally clocked in phase with CR1, but may be delayed
(see Figure 4) to shift the sampled portion of the output
video away from clock feedthroughs.
All CR clocks operate with 50% duty cycle.
Additional details on driving the sensor are provided on Fig-
ure 7.
Output
The signal charge packets from the readout shift register are
transferred serially from the last readout gate (CRLAST),
over the set gate (VSET), to a floating sense node diffusion.
The set gate isolates the sense node diffusion from the last
readout gate and the rest of the readout shift register. As
signal charges accumulate on the floating node diffusion, the
potential of this diffusion decreases. The floating node diffu-
sion is connected to the input of a 2.5-stage low-noise am-
plifier, producing an output signal voltage on the amplifier
output (OS). The floating diffusion is cleared of signal charge
by the reset gate (RST) in preparation for the next signal
charge packet. The voltage level of the floating diffusion af-
ter each reset is determined by the output reset drain volt-
age (VOD). AC coupling the output is recommended to
eliminate the DC offset.
The output signal (OS) requires an off-chip load drawing ap-
proximately 10mA of load current. If the load capacitance
(CLOAD) is greater than 10pF, larger load current (up to the
18mA operating limit) may be required. As the load current
increases, the amplifier bandwidth increases. The amplifier
can also drive larger capacitive loads when the load current
is larger. We recommend however that just enough band-
width be used since larger bandwidth also results in in-
creased noise.
If an off-chip current load is not available, the amplifier out-
put (OS) can be connected to a 1k
W load resistor. The use
of a passive (resistive) load reduces the amplifier gain, re-
sulting in lower responsivity and saturation output signal.
We do not recommend passive loads at data rates greater
than 25 MHz because variations in DC offset will result in
variations in bandwidth.
IL-P3
For product information and updates visit www.dalsa.com
Line Scan Sensors
03-36-00166-06
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