This part is not recommended for new designs
Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI
Bridge for new designs
CY7C68310
Document 38-08030 Rev. *J
Page 8 of 34
Table 5-1. ATACB Field Descriptions
Byte
Field Name
Field Description
0
bVSCBSignature
This field indicates to the CY7C68310 that the ATACB contains a vendor-
specific command block. This value of this filed must match the value in
EEPROM address 0x06h for this vendor-specific command to be recognized.
1
bVSCBSubCommand
This field must be set to 0x024h for ATACB commands.
2
bmATACBActionSelect
This field controls the execution of the ATACB according to the bitfield values:
Bit 7 IdentifyPacketDevice - This bit indicates that the data phase of the
command will contain ATAPI (0xA1h) or ATA (0xECh) IDENTIFY device data.
Setting IdentifyPacketDevice when the data phase does not contain IDENTIFY
device data will result in unspecified device behavior.
0 = Data phase does not contain IDENTIFY device data
1= Data phase contains ATAPI or ATA IDENTIFY device data
Bit 6 UDMACommand - This bit enables supported UDMA device transfers.
Setting this bit when a non-UDMA capable device is attached will result in
undetermined behavior.
0 = Do not use UDMA device transfers (only use PIO mode)
1= Use UDMA device transfers
Bit 5 DEVOverride - This bit determines whether the DEV bit value is taken
from the CY7C68310 configuration data or from the ATACB.
0 = The DEV bit will be taken from EEPROM address 0x05h, bit 5
1= The DEV bit will be taken from the ATACB field 0x0B, bit 4
Bit 4:3 DPErrorOverride - These bits control the Device and Phase Error
override feature. These bits shall not be set in conjunction with bmATACBTask-
FileRead.
00 = Data accesses are halted if a device or phase error is detected
01 = Data accesses are halted if a device error is detected, but not a phase error
10 = Data accesses are halted if a phase error is detected, but not a device error
11 = Neither device or phase errors will result in halting of data accesses
Bit 2 PollAltStatOverride - This bit determines whether or not the Alternate
Status register will be polled and the BSY bit will be used to qualify the start of
ATACB operation.
0 = The AltStat register will be polled until BSY=0 before proceeding with the
ATACB operation
1= The ATACB operation will be executed without polling the AltStat register
Bit 1 DeviceSelectionOverride - This bit determines when the device selection
will be performed in relation to the command register write accesses.
0 = Device selection will be performed prior to command register write
accesses
1 = Device selection will be performed following command register write
accesses
Bit 0 TaskFileRead - This bit determines whether or not the taskfile register
data selected in bmATACBRegisterSelect is returned. If this bit is set, the
dCBWDataTransferLength field must be set to 8.
0 = Execute ATACB command and data transfer (if any)
1 = Only read taskfile registers selected in bmATACBRegisterSelect and return
0x00h for all others. The format of the 8 bytes of returned data is as follows:
Address offset 0x00 (3F6h) - Alternate Status
Address offset 0x01 (1F1h) - Features / Error
Address offset 0x02 (1F2h) - Sector Count
Address offset 0x03 (1F3h) - Sector Number
Address offset 0x04 (1F4h) - Cylinder Low
Address offset 0x05 (1F5h) - Cylinder High
Address offset 0x06 (1F6h) - Device / Head
Address offset 0x07 (1F7h) - Command / Status
3
bmATACBRegisterSelect
This field controls which of the taskfile register read or write accesses occur.
Taskfile read data will always be 8 bytes in length, and unselected register data
will be returned as 0x00h. Register accesses occur in sequential order as
outlined below (0 to 7):
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