W144HT datasheet(6/14 Pages) CYPRESS

6 / 14 page

W144

Document #: 38-07153 Rev. *B

Page 6 of 14

Writing Data Bytes

Each bit in Data Bytes 0–7 controls a particular device function

except for the “reserved” bits, which must be written as a logic

0. Bits are written MSB (most significant bit) first, which is bit 7.

Table 5 gives the bit formats for registers located in Data Bytes

0–7.

Table 6 details additional frequency selections that are

available through the serial data interface.

Table 7 details the select functions for Byte 0, bits 1 and 0.

Data Byte 0

Refer to Table 5

The data bits in Data Bytes 0–7 set internal W144 registers that control

device operation. The data bits are only accepted when the Address Byte

bit sequence is 11010010, as noted above. For description of bit control

functions, refer to Table 5, Data Byte Serial Configuration Map.

5Data Byte 1

6Data Byte 2

7Data Byte 3

8Data Byte 4

9Data Byte 5

Data Byte 6

Data Byte 7

Table 4. Byte Writing Sequence (continued)

Byte

Sequence

Byte Name

Bit Sequence

Byte Description

Table 5. Data Bytes 0-7 Serial Configuration Map

Bit(s)

Affected Pin

Control Function

Bit Control

Default

Pin No.

Pin Name

Data Byte 0

7–

–

(Reserved)

–

SEL_2

See Table 6

–

SEL_1

See Table 6

–

SEL_0

See Table 6

–

Hardware/Software Frequency Select

Hardware

Software

–

SEL_3

See Table 6

1–0

–

Bit 1Bit 0Function (See Table 7 for function details)

00Normal Operation

01(Reserved)

10Spread Spectrum On

11All Outputs Three-stated

Data Byte 1

7–

–

(Reserved)

–

6–

–

(Reserved)

–

5–

–

(Reserved)

–

4–

–

(Reserved)

–

SDRAM_F

Clock Output Disable

Low

Active

2–

–

(Reserved)

–

CPU1

Clock Output Disable

Low

Active

CPU_F

Clock Output Disable

Low

Active

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