W144
Document #: 38-07153 Rev. *B
Page 10 of 14
AC Electrical Characteristics
TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5%;
fXTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated
operating conditions using the stated lump capacitive load at
the clock output; Spread Spectrum clocking is disabled.
Crystal Oscillator
VTH
X1 Input threshold Voltage[6]
VDDQ3 = 3.3V
–
1.65
–
V
CLOAD
Load Capacitance, Imposed on
External Crystal[7]
–14
–
pF
CIN,X1
X1 Input Capacitance[8]
Pin X2 unconnected
–
28
–
pF
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
Except X1 and X2
–
–
5
pF
COUT
Output Pin Capacitance
–
–
6
pF
LIN
Input Pin Inductance
–
–
7
nH
DC Electrical Characteristics TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
CPU Clock Outputs, CPU_F, CPU1 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.6 MHz
CPU = 100.2 MHz
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
tP
Period
Measured on rising edge at 1.25
15
–
15.5
9.98
–
10.5
ns
tH
High Time
Duration of clock cycle above 2.0V
5.6
–
–
3.3
–
–
ns
tL
Low Time
Duration of clock cycle below 0.4V
5.3
–
–
3.1
–
–
ns
tR
Output Rise Edge Rate Measured from 0.4V to 2.0V
1.5
–
4
1.5
–
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1.5
–
4
1.5
–
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at
1.25V
45
–
55
45
–
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V.
Maximum difference of cycle time
between two adjacent cycles.
–
–
200
–
–
200
ps
tSK
Output Skew
Measured on rising edge at 1.25V
–
–
250
250
ps
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
––
3
–
–
3
ms
Zo
AC Output Impedance
Average value during switching
transition. Used for determining series
termination value.
–20
–
–
20–
Ω
Notes:
6. X1 input threshold voltage (typical) is VDDQ3/2.
7. The W144 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF;
this includes typical stray capacitance of short PCB traces to crystal.
8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
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