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AM62A32AMLHAAMB Datasheet(PDF) 48 Page - Texas Instruments |
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AM62A32AMLHAAMB Datasheet(HTML) 48 Page - Texas Instruments |
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48 / 247 page  5.3.2.1 MAIN Domain Table 5-6. CPTS Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] AMB PIN [4] ANF PIN [4] CP_GEMAC_CPTS0_RFT_CLK I CPTS Reference Clock Input B16 B16 CP_GEMAC_CPTS0_TS_COMP O CPTS Time Stamp Counter Compare Output from CPSW3G0 CPTS C16, D22 C16, D22 CP_GEMAC_CPTS0_TS_SYNC O CPTS Time Stamp Counter Bit Output from CPSW3G0 CPTS A17, C22 A17, C22 CP_GEMAC_CPTS0_HW1TSPUSH I CPTS Hardware Time Stamp Push Input to Time Sync Router B15, D21 B15, D21 CP_GEMAC_CPTS0_HW2TSPUSH I CPTS Hardware Time Stamp Push Input to Time Sync Router B22, E15 B22, E15 SYNC0_OUT O CPTS Time Stamp Generator Bit 0 Output from Time Sync Router D17 D17 SYNC1_OUT O CPTS Time Stamp Generator Bit 1 Output from Time Sync Router B16 B16 SYNC2_OUT O CPTS Time Stamp Generator Bit 2 Output from Time Sync Router B17 B17 SYNC3_OUT O CPTS Time Stamp Generator Bit 3 Output from Time Sync Router C18 C18 5.3.3 CSI-2 5.3.3.1 MAIN Domain Table 5-7. CSIRX0 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] AMB PIN [4] ANF PIN [4] CSI0_RXCLKN I CSI Differential Receive Clock Input (negative) AB14 AB14 CSI0_RXCLKP I CSI Differential Receive Clock Input (positive) AB13 AB13 CSI0_RXRCALIB (1) A CSI pin connected to external resistor for on- chip resistor calibration V10 V10 CSI0_RXN0 I CSI Differential Receive Input (negative) W12 W12 CSI0_RXN1 I CSI Differential Receive Input (negative) Y13 Y13 CSI0_RXN2 I CSI Differential Receive Input (negative) AA13 AA13 CSI0_RXN3 I CSI Differential Receive Input (negative) AB11 AB11 CSI0_RXP0 I CSI Differential Receive Input (positive) W13 W13 CSI0_RXP1 I CSI Differential Receive Input (positive) Y14 Y14 CSI0_RXP2 I CSI Differential Receive Input (positive) AA12 AA12 CSI0_RXP3 I CSI Differential Receive Input (positive) AB10 AB10 (1) An external 499Ω ±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is 7.2mW. No external voltage should be applied to this pin. 5.3.4 DDRSS 5.3.4.1 MAIN Domain Table 5-8. DDRSS0 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] AMB PIN [4] ANF PIN [4] DDR0_ACT_n O DDRSS Activation Command N5 N5 DDR0_ALERT_n IO DDRSS Alert H7 H7 DDR0_CAS_n (1) O DDR4 Column Address Strobe / LPDDR4 Chip Select 1B M5 M5 DDR0_PAR O DDRSS Command and Address Parity N2 N2 AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1, AM62A1-Q1 SPRSP77D – MARCH 2023 – REVISED JUNE 2025 www.ti.com 48 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: AM62A7 AM62A7-Q1 AM62A3 AM62A3-Q1 AM62A1-Q1 |
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