PIC16F15213 datasheet(48/408 Pages) MICROCHIP

48 / 408 page

9.5.2

Overflow/Underflow Reset

If the STVREN bit is programmed to ‘1’, the device will be Reset if the stack is PUSHed beyond the sixteenth level or

POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively).

9.6

Indirect Addressing

The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the

INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn

The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are

divided into three memory regions:

• Traditional/Banked Data Memory

• Linear Data Memory

• Program Flash Memory

Figure 9-14. Indirect Addressing PIC16F152

Filename:

10-000044F.vsd

Title:

INDIRECT ADDRESSING

Last Edit:

1/13/2017

First Used:

PIC16(L)F153XX

Note:

0x0000

PC value = 0x000

PC value = 0x7FF

0x87FF

0x0000

0x1FFF

0x2000

0X2FEF

0X2FF0

0x7FFF

0x8000

Reserved

Traditional

Data Memory

Linear

Data Memory

Program

Flash Memory

FSR

Address

Range

Rev. 10-000044F

1/13/2017

PIC16F15225/45

Memory Organization

Preliminary Datasheet

DS20006389B-page 48

PIC16F15213 Datasheet(PDF) 48 Page - Microchip Technology

PIC16F15213 Datasheet(HTML) 48 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL