PIC16F15213 datasheet(102/408 Pages) MICROCHIP

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15.

NVM - Nonvolatile Memory Control

Nonvolatile Memory (NVM) consists of the Program Flash Memory (PFM).

NVM is accessible by using both the FSR and INDF registers, or through the NVMREG register interface.

The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump

rated to operate over the operating voltage range of the device.

NVM can be protected in two ways, by either code protection or write protection.

Code protection (CP bit in the Configuration Words) disables access, both reading and writing, to the PFM via

external device programmers. Code protection does not affect the self-write and erase functionality. Code protection

can only be reset by a device programmer performing a Bulk Erase to the device, clearing all nonvolatile memory,

Configuration bits and User IDs.

Write protection prohibits self-write and erase to a portion or all of the NVM, as defined by the WRTSAF, WRTC,

WRTB and WRTAPP bits of the Configuration Words. Write protection does not affect a device programmer’s ability

to read, write or erase the device.

15.1

Program Flash Memory

Program Flash memory consists of an array of 14-bit words as user memory, with additional words for User ID

information, Configuration words and interrupt vectors. Program memory provides storage locations for:

• User program instructions

• User defined data

Program memory data can be read and/or written to through:

• CPU instruction fetch (read-only)

• FSR/INDF indirect access (read-only)

• NVMREG access

• In-Circuit Serial Programming

™ (ICSP™)

Read operations return a single word of memory. When write and erase operations are done on a row basis, the row

size is defined. Program memory will erase to a logic ‘1’ and program to a logic ‘0’.

It is important to understand the program memory structure for erase and programming operations. Program memory

is arranged in rows. A row consists of 32 14-bit program memory words. A row is the minimum size that can be

erased by user software.

All or a portion of a row can be programmed. Data to be written into the program memory row is written to 14-bit wide

data write latches. These latches are not directly accessible, but may be loaded via sequential writes to the

NVMDATH:NVMDATL register pair.

Important: To modify only a portion of a previously programmed row, the contents of the entire row must

be read. Then, the new data and retained data can be written into the write latches to reprogram the row of

program memory. However, any unprogrammed locations can be written without first erasing the row. In

this case, it is not necessary to save and rewrite the other previously programmed locations.

15.1.1

Program Memory Voltages

The program memory is readable and writable during normal operation over the full VDD range.

15.1.1.1 Programming Externally

The program memory cell and control logic support write and Bulk Erase operations down to the minimum device

operating voltage. Special BOR operation is enabled during Bulk Erase.

PIC16F15225/45

NVM - Nonvolatile Memory Control

Preliminary Datasheet

DS20006389B-page 102

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