CE6313

Data Sheet

10

Intel Corporation

Figure 6 - Viterbi Error Count Measurement

Figure 6 shows the bit errors rising until the maximum programmed value of VIT_ERRPER is reached, when an

interrupt is generated on the IRQ line to advise the host microprocessor that a new value of bit error count has been

loaded into the VIT_ERRCNT [23:0] register. The IRQ line will go high when the IE_FEC register is read by the host

microprocessor. The error count may be expressed as a ratio:

2.4.1.1

Viterbi Error Count Coarse Indication

To assist in the process of aligning the receiver dish aerial, a coarse indication of the number of bit errors being

received can be provided by monitoring the STATUS line with the following set up conditions.

The frequency of the output waveform will be a function of the bit error count (triggering the maximum value

programmed into the VIT_MAXERR[7:0] register and the dish alignment on the satellite. This VIT_MAXERR mode

is enabled by setting the FEC_STAT_EN register bit-0. Figure 7 shows the bit errors rising to the maximum value

programmed and triggering a change of state on the STATUS line.

Error

Count

VIT_ERRCNT[23:0]

VIT_ERRPER

Data Bits

IRQ

0

0

VIT_ERRCNT[23:0]

VIT_ERRPER[7:0] * 262144