8.2.1.1 Design Requirements

For this application, the design requirements are as provided in Table 8-1.

Table 8-1. Design Requirements

DESCRIPTION of INA151

VALUE

Power supply voltage

VS± = ±5V for Cell1Cell16

Battery cell voltage

VBAT = 0V to 4.5V

Common-mode voltage

VCM = 0V to 67.5V

Output Voltage

VOUT = 3.3V

Enable Time

ten=13μs

Filtering

Rfilt=1.2kΩ, Cfilt=150pF

Accuracy target

0.1% at TA=25ºC

DESCRIPTION of ADC in C2000F280025C

VALUE

Full-scale range of ADC

VADC(fs) = VOUT = 3.3V

Acquisition Time

tacq=1μs

Conversion Time

tconv=0.2μs

Sampling Rate per Channel

4.4kSPS

Resolution

12 bits (4096 codes)

LSB Size

+5V / 4096 = 805.66μV/LSB

8.2.1.2 Detailed Design Procedure

The subsequent sections outline guidelines and calculations for dc accuracy analysis DC Accuracy

Calculations, design considerations for external RC filtering in RC Filter Design Consideration and ADC input

protection recommendation. The analysis is provided for the INA151B paired with the ADC of the C2000

(TMS320F280025) Microcontroller from the Figure 8-2 application circuit with given design requirements.

8.2.1.2.1 DC Accuracy Calculations

Table 8-2. INA151B - Typical and Maximum DC Accuracy Calculations for FSR of 4.5V

Error Source

Error Calculation for FSR=4.5V

Spec

(Typ)

Error

(PPM)

Spec

(Max)

Error

(PPM)

Absolute accuracy at 25°C of Cell1

Input stage offset

voltage

VOSI

VOSIFSR×106

200μV

44.4

1200μV

266.7

Common-mode

rejection ratio

CMRRERROR

10VCMCMRR20,VCM = 0V

140dB

0

125dB

0

Gain error from

INA151

GE

GE%×106

0.01%

10

0.03

30

Total error (RSS)

VOSI2+GE2+CMRRERROR2

45.1

268.3

Absolute accuracy at 25°C of Cell16

Input stage offset

voltage

VOSI

VOSIFSR×106

200μV

44.4

1200μV

268.3

Common-mode

rejection ratio

CMRRERROR

10VCMCMRR20,VCM = 67.5V

140dB

1.5

125dB

37.9

Gain error from

INA151

GE

GE%×106

0.01%

10

0.03%

30

INA151

SLVSIL6C – JANUARY 2026 – REVISED APRIL 2026

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