10 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (March 2026) to Revision C (April 2026)

Page

• Changed Offset voltage from ±780μV to ±900μV in Features............................................................................1

• Added "common-mode" to paragraph "... and input impedance.." in Description.............................................. 1

• Change Enable logic input voltage on EN pin from min. VDGND+0.3V to VDGND...........................................4

• Add VDGND-VS/2 to Test Conditions.................................................................................................................6

• Add line for differential-mode voltage with test condition of G=1/4 and TA=-40C to 125C.................................6

• Change typical value of Enable input current from 1.3uA to 1.9uA....................................................................6

• Changed internal node name where pull-up resistors of EN pin is connected from VS+ to VSub................... 17

• Changed from "VREF must stay at or below GND... for linear operating." to "Keep VREF at or below GND

(down to negative supply, thus −5V) for linear operating including temperature and process variation." ....... 20

• Changed from "VREF must stay at or below 2V... for linear operating." to "Keep VREF at or below 2V (down to

negative supply, thus −5V) for linear operating including temperature and process variation." ...................... 20

• Changed Y-axis unit in Fig 7-6 from (V) to (μV)................................................................................................20

• Changed of 450μA to 430μA on the VS+ pin and −460μA on the VS− pin......................................................20

• Changed of 300μA to ±300μA.......................................................................................................................... 20

• Added pull-up resistor R1 in Fig 8-2.................................................................................................................23

• Added section "Output Pullup Resistor in Multiplexer Configuration" with guidance on how to select R1....... 27

• Added paragraph to Layout Guidelines "To minimize measurement errors, limit external series resistance (R1,

R2) to 10Ω or less. Higher resistance values cause higher voltage drop and can reduce measurement

accuracy."......................................................................................................................................................... 29

Changes from Revision A (February 2026) to Revision B (March 2026)

Page

• Changed the device status from Advanced to Production data..........................................................................1

Changes from Revision * (January 2026) to Revision A (February 2026)

Page

• Change HBM value from 2kV to TBD in the ESD Ratings ................................................................................ 4

• Change CBM value from 1kV to TBD in the ESD Ratings ................................................................................ 4

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

INA151

SLVSIL6C – JANUARY 2026 – REVISED APRIL 2026

www.ti.com

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