at TA = 25°C, VS = ±5 V, RL = 10 kΩ, VDGND = VREF = VCM = VS / 2 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

OUTPUT

Output voltage

RL = 10kΩ, TA = –40℃ to 125℃

(V–) + 0.3

(V+) – 0.3

V

CL

Load capacitance

Stable operation

G=1 (A), 2/3 (B)

0.5

nF

G=1/2 (C), 1/4 (D)

0.3

ISC

Short-circuit current

Continuous to Vs/2

Sinking

25

mA

Sourcing

17

FREQUENCY RESPONSE

BW

Bandwidth, –3 dB

CL=100pF

G=1 (A)

620

kHz

G=2/3 (B)

850

G=1/2 (C)

1080

G=1/4 (D)

1600

SR

Slew rate

VDM=±4.7V

2.2

V/µs

tS

Settling time

VDM= ±4.5V-step,

VCM=5V

G=1 (A)

To 0.1%

9

µs

To 1%

4.8

G=2/3 (B)

To 0.1%

7.6

To 1%

3.8

G=1/2 (C)

To 0.1%

10.2

To 1%

2.7

G=1/4 (D)

To 0.1%

8.9

To 1%

1.9

Output enable time

To 0.1%

15

µs

Output disable time(3)

To 0.1%

16

Overload recovery

50% input overload

16

µs

POWER SUPPLY

IQ(VS+)

Quiescent current into VS+

VDM = 0V, EN = HIGH

430

550

µA

IQ(VS–)

Quiescent current into VS–

VDM = 0V, EN = HIGH

–570

–460

µA

IQ

Quiescent current into

VS+/VS–

VDM = 0V, EN = LOW

±300

µA

Quiescent current drift

VDM = 0V, TA = –40℃ to 125℃

–0.07

µA/

℃

ENABLE LOGIC

VEN

Enable input logic low

EN = LOW, DGND

DGND

DGND + 0.9

V

Enable input logic high

EN = HIGH, DGND

DGND + 2

DGND + 5

V

Enable input current

VEN = DGND + 5V

1.9

µA

VDGND

DGND voltage

(VS+) – (VS–) ≤ 12.7V

(VS–)

(VS+) – 2.7

V

VDGND

DGND voltage

(VS+) – (VS–) > 12.7V

(VS–)

(VS–) + 10

V

(1)

Keep both inputs above minimum requirement.

(2)

Specified by design.

(3)

Output disable time depends on the output network of the device which is different for each variant and the load connected. See

Typical Characteristics for more information.

(4)

Asymmetrical input bias current flow, positive IB flowing into the device, negative IB flowing out of the device. See chapter "Low Input

Bias Current" for more information.

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INA151

SLVSIL6C – JANUARY 2026 – REVISED APRIL 2026

Copyright © 2026 Texas Instruments Incorporated

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