M48T248Y datasheet(9/24 Pages) STMICROELECTRONICS

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M48T248Y, M48T248V

OPERATION MODES

Table 6. Operating Modes

Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage

1. See Table 9, page 14 for details.

READ

A READ cycle executes whenever WRITE Enable

(WE) is high and Chip Enable (CE) is low (see Fig-

ure 6). The distinct address defined by the 19 ad-

dress inputs (A0-A18) specifies which of the 512K

bytes of data is to be accessed. Valid data will be

accessed by the eight data output drivers within

the specified Access Time (tACC) after the last ad-

dress input signal is stable, the CE and OE access

times, and their respective parameters are satis-

fied. When CE tACC and OE tACC are not satisfied,

then data access times must be measured from

the more recent CE and OE signals, with the limit-

ing parameter being tCO (for CE) or tOE (for OE) in-

stead of address access.

WRITE

WRITE Mode (see Figure 7, page 10 and Figure 8,

page 11) occurs whenever CE and WE signals are

low (after address inputs are stable). The most re-

cent falling edge of CE and WE will determine

when the WRITE cycle begins (the earlier, rising

edge of CE or WE determines cycle termination).

All address inputs must be kept stable throughout

the WRITE cycle. WE must be high (inactive) for a

minimum recovery time (tWR) before a subsequent

cycle is initiated. The OE control signal should be

kept high (inactive) during the WRITE cycles to

avoid bus contention. If CE and OE are low (ac-

tive), WE will disable the outputs for Output Data

WRITE Time (tODW) from its falling edge.

Figure 6. Memory READ Cycle

Note: WE is high for a READ cycle.

Mode

VCC

DQ7-DQ0

Power

Deselect

4.5V to 5.5V

3.0V to 3.6V

VIH

High-Z

Standby

WRITE

VIL

DIN

Active

READ

VIL

VIH

DOUT

Active

READ

VIL

VIH

High-Z

Active

Deselect

VSO to VPFD (min)

(1)

High-Z

CMOS Standby

Deselect

≤ VSO(1)

High-Z

Battery Back-Up

DQ0 - DQ7

ADDRESSES

DATA OUTPUT

VALID

tOD

tODO

tOE

tRC

tCO

tACC

tCOE

tOH

AI04230

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