M48T248Y, M48T248V

10/24

Figure 7. Memory WRITE Cycle 1

2. If the CE low transition occurs simultaneously with or later than the WE low transition in WRITE Cycle 1, the output buffers remain

in a high impedance state during this period.

3. If the CE high transition occurs simultaneously with the WE high transition, the output buffers remain in a high impedance state

during this period.

AI04231

DQ0–DQ7

ADDRESSES

WE

CE

DATA IN

STABLE

tWR

tOEW

tDH

tDS

tWC

tODW

tWP

tAW

HIGH IMPEDANCE