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C8051F310 Datasheet(PDF) 94 Page - Silicon Laboratories |
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C8051F310 Datasheet(HTML) 94 Page - Silicon Laboratories |
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94 / 228 page  C8051F310/1/2/3/4/5/6/7 94 Rev. 1.7 instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after the completion of the next instruction. 8.3.1. MCU Interrupt Sources and Vectors The MCUs support 14 interrupt sources. Software can simulate an interrupt by setting any interrupt-pend- ing flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associ- ated vector addresses, priority order and control bits are summarized in Table 8.4 on page 96. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). |
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