C8051F310 datasheet(31/228 Pages) SILABS

31 / 228 page

Rev. 1.7

C8051F310/1/2/3/4/5/6/7

1.4.

Programmable Digital I/O and Crossbar

C8051F310/2/4 devices include 29 I/O pins (three byte-wide Ports and one 5-bit-wide Port);

C8051F311/3/5 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port); C8051F316/7

devices include 21 I/O pins (one byte-wide Port, two 6-bit-wide Ports and one 1-bit-wide Port). The

C8051F31x Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be config-

ured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for

push-pull or open-drain output. The “weak pullups” that are fixed on typical 8051 devices may be globally

disabled, providing power savings capabilities.

The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins (See Figure 1.13).

On-chip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the

controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This

allows the user to select the exact mix of general purpose Port I/O and digital resources needed for the

particular application.

Figure 1.13. Digital Crossbar Diagram

XBR0, XBR1,

PnSKIP Registers

Digital

Crossbar

Priority

Decoder

P0.0

P0.7

PnMDOUT,

PnMDIN Registers

UART

Highest

Priority

Lowest

Priority

SYSCLK

SMBus

T0, T1

PCA

CP1

Outputs

SPI

CP0

Outputs

P1.0

P1.7

P2.0

P2.7

P3.0

P3.4

(P0.0-P0.7)

(P1.0-P1.7)

(P2.0-P2.3)

(P2.4-P2.7)

Notes:

1. P3.1–P3.4 only available on the

C8051F310/2/4.

2. P1.6, P1.7, P2.6, P2.7 only

available on the C8051F310/1/2/3/4/5

(P3.0-P3.4)

I/O

Cells

I/O

Cells

I/O

Cells

I/O

Cells

C8051F310 Datasheet(PDF) 31 Page - Silicon Laboratories

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