CS5460

22

DS279PP5

01 = active high level

10 = falling edge (INT is normally high)

11 = rising edge (INT is normally low)

PH[1:0]

Set the phase of the EOUT and EDIR output pin pulse. The EOUT and EDIR pins, on different

phases, can be wire-ORed together as a simple way of summing the frequency of different

parts.

00 = phase 0 (default)

01 = phase 1

10 = phase 2

11 = phase 3

EWA

Allows the output pins of EOUT and EDIR of multiple chips to be connected in a wire-AND, us-

ing an external pull-up device.

0 = normal outputs (default)

1 = only the pull-down device of the EOUT and EDIR pins are active

Gi

Sets the gain of the current PGA

0 = gain is 10 (default)

1 = gain is 50

Res

Reserved. These bits must be set to zero.

PC[3:0]

Phase compensation. A 2’s complement number used to set the delay in the voltage channel.

The bigger the number, the greater the delay in the voltage. The phase adjustment range is

about -2.4 to +2.5 degrees at 60Hz. Each step is about 0.34 degrees at 60Hz.

0000 = Zero degrees phase delay (default)

4.2 Current Offset Register and Voltage Offset Register

Address:

RA[4:0]* = 0x01 (Current Offset Register)

RA[4:0]* = 0x03 (Voltage Offset Register)

Default** = 0.000

The Offset Registers are initialized to zero on reset, allowing the device to function and perform measurements.

The register is loaded after one cycle with the system offset when the proper input is applied and the Calibration

Command is received. The register may be read and stored so the register may be restored with the desired

system offset compensation. The value is in the range ± ½ full scale.

4.3 Current Gain Register and Voltage Gain Register

Address:

RA[4:0]* = 0x02 (Current Gain Register)

RA[4:0]* = 0x04 (Voltage Gain Register)

Default** = 1.000

The Gain Registers are initialized to 1.0 on reset, allowing the device to function and perform measurements.

The register is loaded after one cycle with the system gain when the proper input is applied and the Calibration

Command is received. The register may be read and stored so the register may be restored with the desired

system offset compensation. The value is in the range 0.0

≤ Gain < 4.0.

MSB

LSB

SIGN

.....

MSB

LSB

.....