MPC8313E datasheet(25/92 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

Figure 8 provides the AC test load for TSEC.

Figure 8. TSEC AC Test Load

Figure 9 shows the MII receive AC timing diagram.

Figure 9. MII Receive AC Timing Diagram RMII AC Timing Specifications

RX_CLK clock rise VIL(min) to VIH(max)

tMRXR

1.0—

4.0ns

RX_CLK clock fall time VIH(max) to VIL(min)

tMRXF

1.0—

4.0ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII

receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference

(K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data

input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in

general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.

For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

Table 26. MII Receive AC Timing Specifications (continued)

At recommended operating conditions with LVDDA/LVDDB /NVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

Output

Z0 = 50 Ω

LVDDA/2 or LVDDB/2

RL = 50 Ω

RX_CLK

RXD[3:0]

tMRDXKH

tMRX

tMRXH

tMRXR

tMRXF

RX_DV

RX_ER

tMRDVKH

Valid Data

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