MPC8313E datasheet(27/92 Pages) FREESCALE

27 / 92 page

MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

Figure 11 provides the AC test load.

Figure 11. AC Test Load

Figure 12 shows the RMII receive AC timing diagram.

Figure 12. RMII Receive AC Timing Diagram

8.2.2

RGMII and RTBI AC Timing Specifications

Table 29 presents the RGMII and RTBI AC timing specifications.

REF_CLK clock rise VIL(min) to VIH(max)

tRMXR

1.0

—

4.0

REF_CLK clock fall time VIH(max) to VIL(min)

tRMXF

1.0

—

4.0

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMRDVKH

symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the

tRMX clock reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII receive timing (RMR) with

respect to the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state

or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock

of a particular functional. For example, the subscript of tRMX represents the RMII (RM) reference (X) clock. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

Table 29. RGMII and RTBI AC Timing Specifications

At recommended operating conditions with LVDDA/LVDDB of 2.5 V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

Data to clock output skew (at transmitter)

tSKRGT

–0.5

—

0.5

Data to clock input skew (at receiver) 2

tSKRGT

1.0

—

2.8

Clock cycle duration 3

tRGT

7.2

8.0

8.8

Table 28. RMII Receive AC Timing Specifications (continued)

At recommended operating conditions with NVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol 1

Min

Typical

Max

Unit

Output

Z0 = 50 Ω

NVDD/2

RL = 50 Ω

REF_CLK

RXD[1:0]

tRMRDXKH

tRMX

tRMXH

tRMXR

tRMXF

CRS_DV

RX_ER

tRMRDVKH

Valid Data

MPC8313E Datasheet(PDF) 27 Page - Freescale Semiconductor, Inc

MPC8313E Datasheet(HTML) 27 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL