MPC8313E datasheet(9/92 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Electrical Characteristics

2.1.3

Output Driver Characteristics

Table 3 provides information on the characteristics of the output driver strengths. The values are

preliminary estimates.

2.2

Power Sequencing

The MPC8313E does not require the core supply voltage (VDD and VDDC) and IO supply voltages (GVDD,

LVDD, and OVDD) to be applied in any particular order. Note that during power ramp-up, before the power

supplies are stable and if the I/O voltages are supplied before the core voltage, there might be a period of

time that all input and output pins are actively driven and cause contention and excessive current. In order

to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD

and VDDC) before the I/O voltage (GVDD, LVDD, and OVDD) and assert PORESET before the power

supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise

to 90% of its nominal value before the I/O supplies reach 0.7 V; see Figure 2. Once both the power supplies

(I/O voltage and core voltage) are stable, wait for a minimum of 32 clock cycles before negating

PORESET.

Note that there is no specific power down sequence requirement for the MPC8313E. I/O voltage supplies

(GVDD, LVDD, and OVDD) do not have any ordering requirements with respect to one another.

Table 3. Output Drive Capability

Driver Type

Output Impedance (

Ω)

Supply Voltage

Local bus interface utilities signals

NVDD = 3.3 V

PCI signals

DDR signal

GVDD = 2.5 V

DDR2 signal

GVDD = 1.8 V

DUART, system control, I2C, JTAG,SPI

NVDD = 3.3 V

GPIO signals

NVDD = 3.3 V

eTSEC signals

LVDDA, LVDDB = 2.5/3.3 V

USB Signals

LVDDB = 2.5/3.3 V

MPC8313E Datasheet(PDF) 9 Page - Freescale Semiconductor, Inc