DIA1413/1414

Version 1.0, Sep 2024

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26

2

E2FLT

This bit will be set if the external channel 2 is detected a fault.

1

E1FLT

This bit will be set if the external channel 1 is detected a fault.

0

Reserved

Do not use.

12.10. Channel mask register

The channel mask register is used to determine whether the individual channel is masked or not. When a

channel is masked, the

_____

ALERT pin will not be asserted even when the masked channel detects a fault or out of

limit error. Note that the channel mask can only mask the

_____

ALERT pin in the interrupt mode. No matter the

channel mask bit is set or not, the status registers will be updated normally.

Addr. Type

Register

B7

B6

B5

B4

B3

B2

B1

B0

Default

1Fh

R/W

Channel

mask

Reserved

E3

MASK

E2

MASK

E1

MASK

INT

MASK

00h

Note: R = Read. W = Write.

Bit

Name

Value

Description

7:4

Reserved

Do not use.

3

E3MASK

(DIA1413)

0

(default)

The external channel 3 mask is disabled.

1

The external channel 3 mask is enabled.

2

E2MASK

0

(default)

The external channel 2 mask is disabled.

1

The external channel 2 mask is enabled.

1

E1MASK

0

(default)

The external channel 1 mask is disabled.

1

The external channel 1 mask is enabled.

0

INTMASK

0

(default)

The internal channel mask is disabled.

1

The internal channel mask is enabled.

12.11. Consecutive ALERT register

The consecutive ALERT register is used to choose how many times an out-of-limit (≥ High Limit or < Low Limit)

condition or fault condition have been detected in consecutive measurements before the

_____

ALERT or

______

THERM /ADDR pin is asserted. Additionally, the TIMEOUT bit (B7) is used to enable or disable the SMBus

timeout.

When an out-of-limit condition or fault condition is detected on the same temperature channel in consecutive

measurements, the consecutive alert counter for that channel will be increased by 1. Each counter will be reset if

no out-of-limit condition or fault condition occurs in a consecutive measurement.

When the

_____

ALERT pin is configured in the interrupt mode, if any consecutive alert counter reaches its

programmed value, the STATUS bit for the corresponding channel and the last out-of-limit condition or fault

condition will be set to ‘1’. And the

_____

ALERT pin will be asserted. Then the consecutive alert counter will be