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AT91SAM7S64 Datasheet(PDF) 16 Page - ATMEL Corporation |
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AT91SAM7S64 Datasheet(HTML) 16 Page - ATMEL Corporation |
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16 / 42 page  16 6175BS–ATARM–04-Nov-05 AT91SAM7S Series Summary – Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and locking operations – Interrupt generation in case of forbidden operation 8.4 Peripheral DMA Controller • Handles data transfer between peripherals and memories • Eleven channels: AT91SAM7S256/128/64/321 • Nine channels: AT91SAM7S32 – Two for each USART – Two for the Debug Unit – Two for the Serial Synchronous Controller – Two for the Serial Peripheral Interface – One for the Analog-to-digital Converter • Low bus arbitration overhead – One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory • Next Pointer management for reducing interrupt latency requirements |
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