LXT9782 datasheet(14/78 Pages) INTEL

14 / 78 page

LXT9762/9782 — Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII

Datasheet

Table 2.

LXT97x2 Signal Detect/TP Select Signal Descriptions

9762

Pin#

9782 Pin#

Symbol

Type1

Signal Description2

PQFP

PBGA

101

V16

SD0/TP0

Signal Detect - Ports 0 - 7. Tying the SD/TPn pins High or to a

PECL input sets bit 16.0 = 1 and the respective port is forced to FX

mode. Do not enable Auto-Negotiation if FX mode is selected. In

the absence of an active link, the pin must be pulled High to enable

loopback in FX mode. Do not enable Auto-Negotiation if FX mode is

selected.

The SD/TPn pins have internal pull-downs. When not using FX

mode, SD/TPn pins should be tied to GNDA.

TP Select - Ports 0 - 7. Tying the SD/TPn pins Low sets bit 16.0 = 0

and forces the port to TP mode. The operating mode of each port

can be set to 10BASE-T or 100BASE-TX, half- or full-duplex, and

auto-negotiation or manual control via the hardware control interface

pins as shown in Table 9 on page 27.

100

U13

SD1/TP1

U14

SD2/TP2

161

U15

SD3/TP3

160

162

C16

SD4/TP4

159

161

B17

SD5/TP5

–

160

A17

SD6/TP6

–

159

C17

SD7/TP7

1. Type Column Coding: I = Input, O = Output.

2. Ports 6 and 7 are available only on the LXT9782. These pins are not bonded out on the LXT9762.

Table 3.

LXT97x2 Network Interface Signal Descriptions

9762 Pin#

9782 Pin#

Symbol

Type1

Signal Description 2

PQFP

PBGA

107, 108

W19,W20

TPFOP0, TPFON0

Twisted-Pair/Fiber Outputs, Positive & Negative -

Ports 0-7.

During 100BASE-TX or 10BASE-T operation, TPFO

pins drive 802.3 compliant pulses onto the line.

During 100BASE-FX operation, TPFO pins produce

differential PECL outputs for fiber transceivers.

111, 110

V20, V19

TPFOP1, TPFON1

121, 122

P19, P20

TPFOP2, TPFON2

140, 139

125, 124

N20, N19

TPFOP3, TPFON3

150, 151

136, 137

H19, H20

TPFOP4, TPFON4

154, 153

140, 139

G20, G19

TPFOP5, TPFON5

– , –

150, 151

C19, C20

TPFOP6, TPFON6

– , –

154, 153

B20, B19

TPFOP7, TPFON7

104, 105

Y19, Y20 TPFIP0, TPFIN0

Twisted-Pair/Fiber Inputs, Positive & Neg-

ative - Ports 0-7.

During 100BASE-TX or 10BASE-T opera-

tion, TPFI pins receive differential 100BASE-

TX or 10BASE-T signals from the line.

During 100BASE-FX operation, TPFI pins

receive differential PECL inputs from fiber

transceivers.

115, 114

U20, U19 TPFIP1, TPFIN1

118, 119

R19, R20

TPFIP2, TPFIN2

143, 142

129, 128

M20,

M19

TPFIP3, TPFIN3

146, 147

132, 133

J20, J19

TPFIP4, TPFIN4

157, 156

143, 142

F20, F19

TPFIP5, TPFIN5

– , –

146, 147

D19, D20 TPFIP6, TPFIN6

– , –

157, 156

A20, A19 TPFIP7, TPFIN7

1. Type Column Coding: I = Input, O = Output.

2. Ports 6 and 7 are available only on the LXT9782. These pins are not bonded out on the LXT9762.

LXT9782 Datasheet(PDF) 14 Page - Intel Corporation

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