LXT9782 datasheet(45/78 Pages) INTEL

45 / 78 page

Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII — LXT9762/9782

Datasheet

2.10.2

State Machine

The TAP controller is a 16 state machine driven by the TCK and TMS pins. Upon reset, the

TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS is High for five

TCK periods.

2.10.3

Instruction Register

The IDCODE instruction is always invoked after the state machine resets. The decode logic

ensures the correct data flow to the data registers according to the current instruction. Valid

instructions are listed in Table 14.

2.10.4

Boundary Scan Register

Each BSR cell has two stages. A flip-flop and a latch are used for the serial shift stage and the

parallel output stage. There are four modes of operation as listed in Table 13.

Table 13. BSR Mode of Operation

Mode

Description

Capture

2Shift

Update

System Function

Table 14. Supported JTAG Instructions

Name

Code

Description

Data Register

EXTEST

0000000000000000

External Test

BSR

IDCODE

1111111111111110

ID Code Inspection

ID REG

SAMPLE

1111111111111110

Sample Boundary

BSR

High Z

1111111111001111

Force Float

Bypass

Clamp

1111111111101111

Clamp

BSR

BYPASS

1111111111111111

Bypass Scan

Bypass

Table 15. Device ID Register

31:28

27:12

11:8

7:1

Version

Part ID (hex)

Jedec Continuation Characters

JEDEC ID1

Reserved

0000

2622 (LXT9762)

2636 (LXT9782)

0000

111 1110

1. The JEDEC ID is an 8-bit identifier. The MSB is for parity and is ignored.

Intel’s JEDEC ID is FE (1111 1110) which becomes 111 1110.

LXT9782 Datasheet(PDF) 45 Page - Intel Corporation

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