M7040N datasheet(65/159 Pages) STMICROELECTRONICS

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M7040N

The logical 144-bit search operation is shown in

Figure 46, page 67. The entire table of 144-bit en-

tries is compared to a 144-bit word K (presented

on the DQ Bus in Cycles A and B of the command)

using the GMR and the local mask bits. The GMR

is the 144-bit word specified by the even and odd

global mask pair selected by the GMR Index in the

command’s Cycle A. The 144-bit word K (present-

ed on the DQ Bus in Cycles A and B of the com-

mand) is also stored in both even and odd

comparand register pairs selected by the Com-

parand Register Index in the command’s Cycle B.

The two comparand registers can subsequently

be used by the LEARN command with the even

comparand register stored in an even location,

and the odd comparand register stored in an adja-

cent odd location. The word K (presented on the

DQ Bus in Cycles A and B of the command) is

compared with each entry in the table starting at

location “0.” The first matching entry’s location ad-

dress, “L,” is the winning address that is driven as

part of the SRAM address on the SADR[23:0] lines

(see SRAM ADDRESSING, page 128).

Note: The matching address is always going to an

even address for a 144-bit SEARCH.

The SEARCH command is a pipelined operation

that executes searches at half the rate of the fre-

quency of CLK2X for 144-bit searches in x144-

configured tables. The latency of SADR, CE_L,

ALE_L, WE_L, SSV, and SSF from the 144-bit

SEARCH command cycle (two CLK2X cycles) is

shown in Table 34, page 67.

For a single device in the table with TLSZ = 00, the

latency of the SEARCH from command to SRAM

access cycle is 4. In addition, SSV and SSF shift

further to the right for different values of HLAT, as

specified in Table 35, page 67.

Figure 44. Hardware Diagram for a Table with 1 Device

DQ[71:0]

CMDV, CMD[10:0]

SSF, SSV

SRAM

BHI[2:0]

BHO[2:0]

LHO[1]

LHI

3210

M7040

LHO[0]

654

AI04698

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