M7040N datasheet(26/159 Pages) STMICROELECTRONICS

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M7040N

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The Information Register

Table 12. Information Register Field Descriptions

LRAM

[8]

Last device on this SRAM Bus. When set, this device is the last device on this

SRAM bus in the depth-cascaded table and is the default driver for the SADR, CE_L,

WE_L, and ALE_L signals. In cycles where no M7040N device in a depth-cascaded

table drives these signals, this device drives the signals as follows:

SADR = FFFFFF,

CE_L = 1

WE_L = 1

ALE_L = 1

OE_L is always driven by the device for which this bit is set.

CFG

[24:9]

0000

Database Configuration. The device is internally divided into eight quadrants of 8K x

72, each of which can be configured as 8K x 72, 4K x 144, or 2K x 288 as follows:

00: 8K x 72

01: 4K x 144

10: 2K x 288

11: low power, partition not used for SEARCH

Bits [10:9] apply to configuring the 1st quadrant in the address space.

Bits [12:11] apply to configuring the 2nd quadrant in the address space.

Bits [14:13] apply to configuring the 3rd quadrant in the address space.

Bits [16:15] apply to configuring the 4th quadrant in the address space.

Bits [18:17] apply to configuring the 5th quadrant in the address space.

Bits [20:19] apply to configuring the 6th quadrant in the address space.

Bits [22:21] apply to configuring the 7th quadrant in the address space.

Bits [24:23] apply to configuring the 8th quadrant in the address space.

[71:25]

Reserved.

Field

Range

Initial

Value

Description

Field

Range

Initial Value

Description

Revision

[3:0]

0001

Revision Number. This is the current device revision

number. Numbers start from one and increment by one

for each revision of the device.

Implementation

[6:4]

001

This is the M7040N implementation number.

Reserved

[7]

Reserved.

Device ID

[15:8]

00000100

This is the Device Identification Number.

MFID

[31:16]

0000_0010_0000_1111

Manufacturer ID. This field is the same as the

manufacturer ID and continuation bits in the TAP

controller.

[71:32]

Reserved.

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