M7040N datasheet(17/159 Pages) STMICROELECTRONICS

17 / 159 page

17/159

M7040N

Table 7. AC Timing Parameters with CLK2X

Note: 1. Valid for Ambient Operating Temperature: TA =0to70°C; VDD =1.5V.

2. Values are based on 50% signal levels.

3. Based on an AC load of CL = 30pF (see Figure 5, Figure 6, and Figure 7, page 13).

4. These parameters are sampled and not 100% tested, and are based on an AC load of 5pF.

Row

Sym

M7040N-

066

M7040N-

083

M7040N-

100

Unit

Description(1)

(VDDQ =

3.3V, 2.5V)

(VDDQ =

3.3V, 2.5V,

1.8V)

(VDDQ =

3.3V, 2.5V)

Min

Max

Min

Max

Min

Max

fCLOCK

133

166

200

MHz CLK2X frequency

tCLOK

0.5

PLL lock time

tCKHI

3.0

2.4

2.0

CLK2X high pulse(2)

tCKLO

3.0

2.4

2.0

CLK2X low pulse(2)

tISCH

2.5

1.8

1.5

Input Setup Time to CLK2X rising edge(2)

tIHCH

0.6

0.5

Input Hold Time to CLK2X rising edge(2)

tICSCH

4.2

3.5

3.0

Cascaded Input Setup Time to CLK2X rising

edge(2)

tICHCH

0.6

0.5

Cascaded Input Hold Time to CLK2X rising edge(2)

tCKHOV

8.5

7.0

6.5

Rising edge of CLK2X to LHO, FULO, BHO, FULL

valid(3)

tCKHDV

9.0

7.5

7.0

Rising edge of CLK2X to DQ valid(3)

tCKHDZ

8.5

7.0

6.5

Rising edge of CLK2X to DQ high-Z(4)

tCKHSV

9.0

7.5

7.0

Rising edge of CLK2X to SRAM bus valid(3)

tCKHSHZ

6.5

6.0

5.5

Rising edge of CLK2X to SRAM bus high-Z(4)

tCKHSLZ

7.0

6.5

6.0

Rising edge of CLK2X to SRAM bus low-Z(4)

M7040N Datasheet(PDF) 17 Page - STMicroelectronics

M7040N Datasheet(HTML) 17 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL