DIO8833

Version 1.0, Nov 2025

www.dioo.com

© 2025 Dioo Microcircuits Co., Ltd. Jiangsu

17



Cooling mode: VVTEC = 1.25 V + 0.2 × (VOL - VOS)



Heating mode: VVTEC = 1.25 V - 0.2 × (VOS - VOL)

where VVTEC represents the XTEC pin output voltage.

8.5. High accuracy voltage reference

The DIO8833 has an integrated 2.5 V reference voltage with 0.6% accuracy. When the input voltage (VIN)

exceeds 2.7 V, the VREF output remains stable and unaffected by the EN or SD input or the I2C registers.

8.6. Power stage

The DIO8833 provides an H-bridge integrated power stage, including an LDO and Buck converter. The

power stage activates if all of the following conditions are met:



VIN exceeds UVLO level.



EN is high.



SD is high.



I2C_ON bit = 1.

8.7. Enable pin (EN)

The device is enabled when the EN pin voltage exceeds 0.825 V, provided all other conditions (including

VIN > 2.6 V for UVLO) are satisfied. Upon enable, the internal discharge paths first discharge any residual

TEC bias voltage to 0 V, followed by the soft-start ramp-up of the VOL and VOS outputs. The EN pin

incorporates internal 6 MΩ pull-down resistor; if left unconnected, the pin is held low, forcing the device into

disabled state.

8.8. Shutdown pin (SD)

The device enters shutdown mode when the SD pin is driven low. This pin incorporates an internal 1.3 MΩ

pull-down resistor to ensure proper default state. A rising edge on the SD pin initiates device power-up

following a 25 ms delay period to ensure stable initialization.

8.9. TEC voltage limit

The DIO8833 features integrated TEC voltage limit protection with programmable thresholds set by I2C

interface (Reg03 VLIM_HEAT[D5:D0] for heating, Reg04 VLIM_COOL[D5:D0] for cooling) without requiring

external components. The protection provides adjustable limits from 0 mV to 5.5 V in 97.6 mV steps (see

Table 3). When the TEC voltage exceeds the programmed limit, the Buck converter regulates VOS output to

the threshold value independently of CTL control, preventing hazardous operation (see Figure 36).

An additional fixed internal secondary limit (typically 1 V above the programmed limit) provides protection

during fault conditions such as TEC terminal shorts to VIN or GND. Upon exceeding the secondary limit, the

device immediately terminates switching and enters hiccup mode for system protection. This two-stage

protection architecture ensures both controlled regulation during normal operation and failsafe response to

severe fault conditions.