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R7FA6T2AB3CFP Datasheet(PDF) 40 Page - Renesas Technology Corp |
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R7FA6T2AB3CFP Datasheet(HTML) 40 Page - Renesas Technology Corp |
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40 / 101 page  Output stopping signal from GPT*1 GPT output pins Outputs disabled tPOEGDE Note 1. GPT32n.GTST.DTEF (dead time error flag), GPT32n.GTST.OABLF (simultaneous low output flag), or GPT32n.GTST.OABHF (simultaneous high output flag) Figure 2.17 Output Disable Time for POEG in Response to Detection of the Output Stopping Signal from GPT ACMPHSn edge detection signal (n = 0 to 3) GPT output pins Outputs disabled tPOEGDC Figure 2.18 Output Disable Time for POEG in Response to Edge Detection Signal from ACMPHS GPT output pins Outputs disabled tPOEGDS POEGGn.SSF bit (n = A to D) Figure 2.19 Output Disable Time for POEG in Response to the Register Setting Oscillation stop detection signal (internal signal) GPT output pins Outputs disabled tPOEGDOS Main clock Figure 2.20 Output Disable Time of POEG in Response to the Oscillation Stop Detection RA6T2 Datasheet 2. Electrical Characteristics R01DS0400EJ0150 Rev.1.50 Jul 2, 2025 Page 40 of 101 |
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