NJW1201A

– 6 –

CHARACTERISTICS OF BUS LINES (SDA,SCL) FOR I

2C-BUS DEVICES

Standard mode

Fast mode

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

UNIT

SCL clock frequency

fSCL

-

-

100

-

-

400

kHz

Hold time (repeated) START condition.

tHD:STA

4.0

-

-

0.6

-

-

µs

Low period of the SCL clock

tLOW

4.7

-

-

1.3

-

-

µs

High period of the SCL clock

tHIGH

4.0

-

-

0.6

-

-

µs

Set-up time for a repeated START condition

tSU:STA

4.7

-

-

0.6

-

-

µs

Data hold time

NOTE)

tHD:DAT

0

-

-

0

-

-

µs

Data set-up time

tSU:DAT

250

-

-

100

-

-

ns

Rise time of both SDA and SCL signals

tr

-

-

1000

-

-

300

ns

Fall time of both SDA and SCL signals

tf

-

-

300

-

-

300

ns

Set-up time for STOP condition

tSU:STO

4.0

-

-

0.6

-

-

µs

Bus free time between a STOP and START condition

tBUF

4.7

-

-

1.3

-

-

µs

Capacitive load for each bus line

Cb

-

-

400

-

-

400

pF

Noise margin at the Low level

VnL

0.5

-

-

0.5

-

-

V

Noise margin at the High level

VnH

1

-

-

1

-

-

V

Cb ; total capacitance of one bus line in pF.

NOTE). Data hold time : tHD:DAT

Please hold the Data Hold Time (tHD:DAT) to 300ns or more to avoid status of unstable at SCL falling edge.

The SDA block in the NJW1201A does not hold data. Add external data-delay-circuit of the SDA terminal, in case of not

providing a hold time of at least 300nsec for the SDA in the master device.

The time-consists of the data-delay-circuit of the SDA terminal are as follows.

(a) Low level

High level :

TLH ≈ RP*CD

(b) High level

Low level :

THL ≈ RD*CD

In addition, Schottky barrier diode (SBD) influences a Low level at the Acknowledge. Therefore choose the low forward

voltage (Vf) as much as possible.

MASTER

SCL

SDA

VDD

RP

RP

RD

SBD

CD

NJW1201A