RX72N datasheet(142/179 Pages) RENESAS

142 / 179 page

R01DS0343EJ0120 Rev.1.20

Page 142 of 179

Nov 15, 2023

RX72N Group

2. Electrical Characteristics

2.4.7.14

PMGI

n = 0, 1

Figure 2.78

Timing of Serial Management Access

Table 2.43

PMGI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

ICLK = PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the drive capacity control register.

Item

Symbol

Min.

Max.

Unit

Test

Conditions

PMGI

PMGIn_MDC output cycle

tMDC

—

Figure 2.78

PMGIn_MDIO setup time (relative to PMGIn_MDC↑)tSMDIO

—

PMGIn_MDIO hold time (relative to PMGIn_MDC↑)tHMDIO

0—

PMGIn_MDIO output delay time (relative to PMGIn_MDC↑)tDMDIO

020

tSMDIO

PMGIn_MDC

(output)

PMGIn_MDIO

(input)

tHMDIO

tMDC

PMGIn_MDIO

(output)

tDMDIO

PMGIn_MDC

(output)

PMGIn_MDIO

(input)

PMGIn_MDIO

(output)

(n = 0, 1)

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