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RZ/G2L Datasheet(PDF) 10 Page - Renesas Technology Corp |
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RZ/G2L Datasheet(HTML) 10 Page - Renesas Technology Corp |
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10 / 74 page ![]() RZ/G2L Group, RZ/G2LC Group 1. Overview R01DS0484EJ0110 Rev.1.10 Page 10 of 74 May 30, 2025 Item Description General PWM Timer (GPT) [RZ/G2L] ● 32 bits × 8 channels [RZ/G2LC] ● 32 bits × 6 channels [RZ/G2L RZ/G2LC] ● Counting up or down (sawtooth wave), counting up and down (triangular wave) selectable for all channels ● Independent selectable for each channel ● 2 input/output pins per channel ● 2 output compare / input capture registers per channel ● For the 2 output compare / input capture registers of each channel, 4 registers are provided as buffer registers and are capable of operating as comparison registers when buffering is not in use ● In output compare operation, buffer switching can be at peaks or troughs, enabling the generation of laterally asymmetrically PWM waveforms ● Registers for setting up frame intervals on each channel (with capability for generating interrupts on overflow or underflow) ● Generation of dead times in PWM operation ● Synchronous start / stop / clear of counters on arbitrary channels ● Starting, stopping, and clearing up/down counters in response to a maximum of eight events ● Starting, stopping, and clearing up/down counters in response to input level comparison ● Starting, stopping, and clearing up/down counters in response to a maximum of four external triggers ● Output pin invalidation functions due to dead time error or detection of short circuit between output pins ● Digital filter functions for the input capture and external trigger pins Port Output Enable for GPT (POEG) [RZ/G2L RZ/G2LC] ● Output prohibition control of the GPT waveform output pin ● Activation with up to four input pins ● Activation by dead time error detection or output short detection ● Activation by register write Watchdog Timer (WDT) [RZ/G2L RZ/G2LC] ● 3 channels ● A counter overflow can reset the LSI ● CPU parity error can reset the LSI General Timer (GTM) [RZ/G2L RZ/G2LC] ● 32 bits × 3 channels ● Two operating modes – Interval timer mode – Free-running comparison mode |
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