RZSLASHG2E datasheet(112/169 Pages) RENESAS

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RZ/G Series, 2nd Generation Datasheet

Section 3. Electrical Characteristics

R01DS0483EJ0101 Rev.1.01

Page 112 of 169

Jun 30, 2025

3.19 SCIF

Table 3.19.1 SCIF Signal Timing

Conditions: VDDQ33 = VDDQVA_SDn = 3.3 ± 0.2 V [RZ/G2H, RZ/G2M V1.3, RZ/G2M V3.0, RZ/G2N],

VDDQ33 = 3.3 ± 0.3 V [RZ/G2E],

GND = VSS = 0 V, Tc = -40 to +115 °C [RZ/G2H, RZ/G2M V1.3],

Ta = −40 to +85 °C [RZ/G2M V3.0, RZ/G2N, RZ/G2E],

Tj = -40 to +115 °C [RZ/G2M V3.0, RZ/G2N, RZ/G2E], CL = 30 pF

Item

Symbol

Min.

Typ.

Max.

Unit

Figures

Input clock cycle (asynchronous)

tSCYC

—

tCYC

Figure 3.19.1

Input clock cycle (synchronous)

tSCYC

—

tCYC

Input clock pulse width

tSCKW

0.4

—

0.6

tSCYC

Input clock rise time

tSCKr

—

0.8

tCYC

Input clock fall time

tSCKf

—

0.8

tCYC

Transmit data delay time

tTXD

—

tCYC

Figure 3.19.2

Receive data setup time (synchronous)

tRXS

—

tCYC

Receive data hold time (synchronous)

tRXH

—

tCYC

Note:

RZ/G2H, RZ/G2M V1.3, RZ/G2M V3.0, RZ/G2N: tCYC is for one cycle of the S3D4ϕ clock.

RZ/G2E: tCYC is for one cycle of the S3D4Cϕ clock.

Figure 3.19.1 Input Clock Timing

Figure 3.19.2 Input/output Timing in Synchronous Mode

BRGCLK

(Internal signal)

Note: The output signal (BRGCLK) of the external baud rate generator (BRG) is an SCIF internal signal.

Set the input signal and the DL and CKS registers of the BRG so that the BRGCLK signal can satisfy the above specification.

tSCYC

tSCKW

tSCKf

tSCKr

RZ/G2H

RZ/G2M V1.3

RZ/G2N

RZ/G2E

RZ/G2M V3.0

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