ADATE320 datasheet(70/78 Pages) AD

70 / 78 page

Data Sheet

ADATE320

SPI REGISTER MEMORY MAP AND DETAILS

analog.com

Rev. C | 70 of 78

Table 29. SPI Register Memory Map

CH[1:0]1, 2

Address (ADDR[6:0])

R/W

DATA[15:0]3

Reset Value

0x5D

R/W

DDDD

POHx (PPMU comparator MI) c coefficient

0x8000

0x5E

R/W

DDDD

POLx (PPMU comparator MI) c coefficient

0x8000

0x5F

XXXX

Reserved

0x60

XXXX

Reserved

0x61

R/W

DDDD

POHx (PPMU comparator MI Range A) m coefficient

0xFFFF

0x62

R/W

DDDD

POHx (PPMU comparator MI Range B) m coefficient

0xFFFF

0x63

R/W

DDDD

POHx (PPMU comparator MI Range C) m coefficient

0xFFFF

0x64

R/W

DDDD

POHx (PPMU comparator MI Range D) m coefficient

0xFFFF

0x65

R/W

DDDD

POHx (PPMU comparator MI Range E) m coefficient

0xFFFF

0x66

R/W

DDDD

POLx (PPMU comparator MI Range A) m coefficient

0xFFFF

0x67

R/W

DDDD

POLx (PPMU comparator MI Range B) m coefficient

0xFFFF

0x68

R/W

DDDD

POLx (PPMU comparator MI Range C) m coefficient

0xFFFF

0x69

R/W

DDDD

POLx (PPMU comparator MI Range D) m coefficient

0xFFFF

0x6A

R/W

DDDD

POLx (PPMU comparator MI Range E) m coefficient

0xFFFF

0x6B to 0x7F

XXXX

Reserved

1 X means don’t care for the respective field.

2 CC represents two contiguous binary channel bits.

3 DDDD represents four-digit hexadecimal data.

4 The active load VIOHx and VIOLx voltage offsets are guaranteed to be nonzero and positive. These offsets result in a nonzero current for each IOHx and IOLx level

following valid reset sequence and prior to calibration. Furthermore, the active load is forced into the active on state following a reset, which facilitates a soft connect of the

DUTx pin to VCOMx = 0.0 V following a valid reset sequence (with small but nonzero IOHx and IOLx currents).

Reserved bits in any register are undefined. In some cases, a

physical but unused memory bit may be present.

Any SPI read operation from a reserved bit or register results in an

unknown but deterministic readback value. Any SPI write operation

to a reserved bit or register results in no action.

A write to a control bit or control register defined only on Channel 0

must be addressed to Channel 0. Any such write that is addressed

to only Channel 1 is ignored if no register or control bit is defined on

Channel 1.

Furthermore, any such write that is addressed to both Channel 0

and Channel 1 (as a multichannel write) proceeds as if the write

is addressed to both Channel 0 and Channel 1. If no register or

control bit is defined at Channel 1, data addressed to the undefined

Channel 1 is ignored. If a register or control bit is defined at

Channel 1, it is filled as part of the multichannel write.

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