ST10R172L datasheet(44/68 Pages) STMICROELECTRONICS

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ST10R172L - ELECTRICAL CHARACTERISTICS

Data hold after RD

rising edge

t18

–0

–

Data float after RD rising

edge 12))

t19

–

15 +

–

2TCL - 5 +

Data valid to WR

t22

13 +

–

2TCL - 7 +

–ns

Data hold after WR

t23

13 +

–

2TCL - 7+

–ns

ALE rising edge after RD,

t25

10 +

–

2TCL - 10 +

tF –ns

Address hold after RD, WR

t27

10 +

–

2TCL - 10 +

tF –ns

Latched CS setup to ALE

t38

-7 +

3 +

-7 +

3 +

Unlatched CS setup to

ALE

t38u CC 3 + tA

–

TCL - 7 +

–ns

Latched CS low to Valid

Data In

t39

–

tC + 2tA

–

3TCL - 17

tC + 2tA

Unlatched CS low to Valid

Data In

t39u SR –

tC + 2tA

–

4TCL - 17

tC + 2tA

Latched CS hold after RD,

t40

20 +

–

3TCL - 10 +

tF –ns

Unlatched CS hold after

RD, WR

t40u CC 10 + tF

–

2TCL - 10 +

tF –ns

ALE fall. edge to RdCS,

WrCS (with RW delay)

t42

7 +

–

TCL - 3 +

–ns

ALE fall. edge to RdCS,

WrCS (no RW delay)

t43

-3 +

–

-3 +

–ns

Address float after RdCS

(with RW delay)1

t44

–

Address float after RdCS

(no RW delay)1

t45

–

131

–

TCL + 31

Parameter

Symbol

Max. CPU Clock

= 50 MHz

Variable CPU Clock

1/2TCL = 1 to 50 MHz

min.

max.

min.

max.

Table 14 Multiplexed bus

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