ST7265X datasheet(92/166 Pages) STMICROELECTRONICS

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ST7265x

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11.5 PWM/BRM GENERATOR (DAC)

11.5.1 Introduction

This PWM/BRM peripheral includes a 6-bit Pulse

Width Modulator (PWM) and a 4-bit Binary Rate

Multiplier (BRM) Generator. It allows the digital to

analog conversion (DAC) when used with external

filtering.

Note: The number of PWM and BRM channels

available depends on the device. Refer to the de-

vice pin description and register map.

11.5.2 Main Features

Fixed frequency: fCPU/64

Resolution: T

CPU

Steps of V

DD/2

10 (5mV if V

DD=5V)

11.5.3 Functional Description

The 10 bits of the 10-bit PWM/BRM are distributed

as 6 PWM bits and 4 BRM bits. The generator con-

sists of a 10-bit counter (common for all channels),

a comparator and the PWM/BRM generation logic.

PWM Generation

The counter increments continuously, clocked at

internal CPU clock. Whenever the 6 least signifi-

cant bits of the counter (defined as the PWM coun-

ter) overflow, the output level for all active chan-

nels is set.

The state of the PWM counter is continuously

compared to the PWM binary weight for each

channel, as defined in the relevant PWM register,

and when a match occurs the output level for that

channel is reset.

This Pulse Width modulated signal must be fil-

tered, using an external RC network placed as

close as possible to the associated pin. This pro-

vides an analog voltage proportional to the aver-

age charge passed to the external capacitor. Thus

for a higher mark/space ratio (high time much

greater than low time) the average output voltage

is higher. The external components of the RC net-

work should be selected for the filtering level re-

quired for control of the system variable.

Each output may individually have its polarity in-

verted by software, and can also be used as a log-

ical output.

Figure 52. PWM Generation

COUNTER

COMPARE

VALUE

OVERFLOW

000

PWM OUTPUT

CPU x 64

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