ST7SCR datasheet(50/102 Pages) STMICROELECTRONICS

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ST7SCR

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USB INTERFACE (Cont’d)

Bits 1:0 = STAT_RX [1:0]

Status bits, for reception

transfers.

These bits contain the information about the end-

point status, which are listed below:

Table 16. Reception Status Encoding

These bits are written by software. Hardware sets

the STAT_RX and STAT_TX bits to NAK when a

correct transfer has occurred (CTR=1) addressed

to this endpoint, so the software has the time to ex-

amine the received data before acknowledging a

new transaction.

Note 1:

If a SETUP transaction is received while the status

is different from DISABLED, it is acknowleded and

the two directional status bits are set to NAK by

hardware.

Note 2:

When a STALL is answered by the USB device,

the two directional status bits are set to STALL by

hardware.

ENDPOINT

TRANSMISSION

(EP1TXR,

EP2TXR,

EP3TXR,

EP4TXR,

EP5TXR)

Read/Write

Reset value: 0000 0000 (00h)

This register is used for controlling Endpoint 1, 2,

3, 4 or 5 transmission. Bits 2:0 are also reset by a

USB reset, either received from the USB or forced

through the FRES bit in the USBCTLR register.

Bits [7:4] = Reserved, forced by hardware to 0.

Bit 3 = CTR_TX

Correct Transmission Transfer.

This bit is set by hardware when a correct transfer

operation is performed in transmission. This bit

must be cleared after the corresponding interrupt

has been serviced.

0: No CTR in transmission on Endpoint 1, 2, 3, 4 or

1: Correct transfer in transmission on Endpoint 1,

2, 3, 4 or 5

Bit 2 = DTOG_TX

Data Toggle, for transmission

transfers.

This bit contains the required value of the toggle

bit (0=DATA0, 1=DATA1) for the next data packet.

DTOG_TX toggles only when the transmitter has

received the ACK signal from the USB host.

DTOG_TX and DTOG_RX are normally updated

by hardware, at the receipt of a relevant PID. They

can be also written by the user, both for testing

purposes and to force a specific (DATA0 or

DATA1) token.

Bits [1:0] = STAT_TX [1:0]

Status bits, for trans-

mission transfers.

These bits contain the information about the end-

point status, which is listed below

Table 17. Transmission Status Encoding

These bits are written by software, but hardware

sets the STAT_TX bits to NAK when a correct

transfer has occurred (CTR=1) addressed to this

endpoint. This allows software to prepare the next

set of data to be transmitted.

STAT_RX1 STAT_RX0

Meaning

DISABLED: no function can be

executed on this endpoint and

messages related to this end-

point are ignored.

STALL: the endpoint is stalled

and all reception requests re-

sult in a STALL handshake.

NAK: the endpoint is NAKed

and all reception requests re-

sult in a NAK handshake.

VALID: this endpoint is ena-

bled (if an address match oc-

curs, the USB interface

handles the transaction).

0000

CTR_T

DTOG

_TX

STAT_

TX1

STAT_

TX0

STAT_TX1 STAT_TX0

Meaning

DISABLED: transmission

transfers cannot be executed.

STALL: the endpoint is stalled

and all transmission requests

result in a STALL handshake.

NAK: the endpoint is naked

and all transmission requests

result in a NAK handshake.

VALID: this endpoint is ena-

bled for transmission.

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