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AT91SAM7A2-AI Datasheet(PDF) 33 Page - ATMEL Corporation |
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AT91SAM7A2-AI Datasheet(HTML) 33 Page - ATMEL Corporation |
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33 / 369 page  33 PRELIMINARY AT91SAM7A2 6021A–ATARM–07/04 • 0 wait states 1/2 cycle • 1 wait state 1 cycle For each additional wait state programmed, an additional cycle is added. Wait state with Read Cycle The read cycle is delayed one cycle for each wait state programmed. In early mode, NOE/NRD goes low at the start of the read cycle while in standard mode, this signal goes low at the half of the first cycle. The following figure shows a read cycle with one wait state. Figure 19. Read Cycle with One Wait State The following figure shows a read cycle with two wait states. Figure 20. Read Cycle with Two Wait States Wait State with Write Cycle The write cycle is delayed one cycle for each wait state programmed. NWE (or NWR0, NWR1) goes high one half cycle before the end of the write cycle. The following figure shows a write cycle with one wait state. Figure 21. Write Cycle with One Wait State Address Valid Address NCS NOE/NRD Address Valid Address NCS NOE/NRD Address Valid Address NCS NWE |
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