AT91SAM7A2-AI datasheet(40/369 Pages) ATMEL

40 / 369 page

PRELIMINARY

AT91SAM7A2

6021A–ATARM–07/04

Timings

Table 25 below and Table 26 on page 41 show the minimum and maximum timings for

external memory Read/Write cycles (valid over the recommended operating conditions)

for a capacitive load of 15 pF and 30 pF. These timings are represented on the relevant

waveform.

Table 25. Timings for Read Access

Read Access

Load = 15pf

Load = 30pf

MIN

TYP

MAX

MIN

TYP

MAX

ADCRDV2

Address Change to Read Data Valid

(Read/Write Memory, 0 Wait State,

standard read)

CYCLE - 27 ns

CYCLE - 31 ns

ADCRDV1

Address Change to Read Data Valid

(All other cases)

(1 + NWS) *

CYCLE - 15 ns

(1 + NWS) *

CYCLE - 17 ns

CSLRDV

Chip Select Low to Read Data Valid

(1 + NWS) *

CYCLE - 14 ns

(1 + NWS) *

CYCLE - 16 ns

OELRDV1

Output Enable Low to Read Data Valid

(standard read)

(0.5 + NWS) *

CYCLE - 12 ns

(0.5 + NWS) *

CYCLE - 13 ns

OELRDV2

Output Enable Low to Read Data Valid

(early read)

(1 + NWS) *

CYCLE - 12 ns

(1 + NWS) *

CYCLE - 13 ns

BSLRDV2

Byte Select Low to Read Data Valid

(Read/Write Memory, 0 Wait State,

standard read)

(1 + NWS) *

CYCLE - 26 ns

(1 + NWS) *

CYCLE - 31 ns

BSLRDV1

Byte Select Low to Read Data Valid

(all other cases)

(1 + NWS) *

CYCLE - 16 ns

(1 + NWS) *

CYCLE - 18 ns

Data Hold-time from Address

Change/NCS High/NOE High

DHZOEL1

Data Hi-Z to Output Enable Low

(previous is a write cycle - standard

read)

- 2 ns

- 3 ns

DHZOEL2

Data Hi-Z to Output Enable Low

(previous is a write cycle - early read)

0.5 * t

CYCLE

- 1 ns

0.5 * t

CYCLE

- 3 ns

DHZCSL

Data Hi-Z to Chip Select Low

(previous is a write cycle - standard)

0.5 * t

CYCLE +

1 ns

0.5 * t

CYCLE

+ 1 ns

AT91SAM7A2-AI Datasheet(PDF) 40 Page - ATMEL Corporation

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